ETISS 0.8.0
ExtendableTranslatingInstructionSetSimulator(version0.8.0)
RISCV64Arch.cpp
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1 // This file was generated on Mon Aug 03 15:02:40 CEST 2020
2 // If necessary please modify this file according to the instructions
3 // Contact: eda@tum
4 
5 /*********************************************************************************************************************************
6 
7 * Modification guidelines:
8 
9  1. The initial value of SP register should be initialized by ctr0.S/board.S. If not, it could be initialized
10  through utility class etiss::VirtualStruct::Field.
11 
12  2. Debug mode print out all assignment results. GDB in 8 is prefered.
13 
14  3. Manually copy the content in bracket ["return ETISS_RETURNCODE_CPUFINISHED; \n"] to terminating instruction,
15  otherwise the emulation can not be ended.
16 
17  4. If subset of encoding error occurs, it means the format of the encoding in the input model was not appropriate
18 
19  5. If the PC register points to wrong address, please notice that some assembly may cause branch operation
20  implicitly such as "MOV Rd Rn" in ARMv6-M
21 
22  6. If a variable is the result of dynamic slicing such as, var_1 = var_2<Hshift-1..Lshift-2>, the size would be
23  calculated during process (if possible), otherwise it is assumed to be the register size. Problems may occur when
24  var_1 encounters bit manipulation such as "~" due to bit expansion. To change the nml model with explicit slicing
25  e.g var_1 = val_2<3..0> or avoid bit manipulation for dynamic sliced variable. Otherwise, you have to manually
26  correct it.
27 
28  7. Implementation dependent functionalities such as exception handling should be manully added. Corresponding interfaces
29  are provided in RISCV64ArchSpecificImp.h
30 
31  8. RISCV64GDBCore.h provides the GDBCore class to support gdb flavor debugging feature, modify iy if in need.
32 
33  *********************************************************************************************************************************/
34 
35 #include "RISCV64Arch.h"
36 #include "RISCV64ArchSpecificImp.h"
37 
38 #define RISCV64_DEBUG_CALL 0
39 #define RISCV64_Pipeline1 0
40 #define RISCV64_Pipeline2 0
41 using namespace etiss ;
42 using namespace etiss::instr ;
43 
44 // Debug
45 int32_t tlb_overlap_handler(int32_t fault, MMU *mmu, uint64_t vma, MM_ACCESS access)
46 {
47  return etiss::RETURNCODE::NOERROR;
48 }
49 
50 RISCV64Arch::RISCV64Arch():CPUArch("RISCV64")
51 {
52  headers_.insert("Arch/RISCV64/RISCV64.h");
53 }
54 
55 const std::set<std::string> & RISCV64Arch::getListenerSupportedRegisters()
56 {
57  return listenerSupportedRegisters_;
58 }
59 
60 ETISS_CPU * RISCV64Arch::newCPU()
61 {
62  ETISS_CPU * ret = (ETISS_CPU *) new RISCV64() ;
63  resetCPU (ret, 0);
64  return ret;
65 }
66 
67 void RISCV64Arch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
68 {
69  memset (cpu, 0, sizeof(RISCV64));
70  RISCV64 * riscv64cpu = (RISCV64 *) cpu;
71 
72  if (startpointer) cpu->instructionPointer = *startpointer;
73  else cpu->instructionPointer = 0x0; // reference to manual
74  cpu->mode = 1;
75  cpu->cpuTime_ps = 0;
76  cpu->cpuCycleTime_ps = 31250;
77  #if RISCV64_Pipeline1 || RISCV64_Pipeline2
78  //Initialize resources measurements
79  cpu->resources[0] = "I_RAM";
80  cpu->resources[1] = "IF";
81  cpu->resources[2] = "ID";
82  cpu->resources[3] = "Multiplier1";
83  cpu->resources[4] = "ReadPorts";
84  cpu->resources[5] = "ALU";
85  cpu->resources[6] = "D_RAM";
86  cpu->resources[7] = "WB";
87  cpu->resources[8] = "Multiplier2";
88  for(int i = 0; i < 9; i = i + 1){
89  cpu->resourceUsages[i] = 0;
90  cpu->cycles[i] = 0;
91  }
92  #endif
93 
94  // Instantiate the pointers in order to avoid segmentation fault
95  for(int i = 0; i < 32; i ++)
96  {
97  riscv64cpu->ins_X[i] = 0;
98  riscv64cpu->X[i] = & riscv64cpu->ins_X[i];
99  }
100 
101  // Initialize the registers and state flags;
102  riscv64cpu->ZERO = 0;
103  riscv64cpu->X[0] = & (riscv64cpu->ZERO);
104  riscv64cpu->RA = 0;
105  riscv64cpu->X[1] = & (riscv64cpu->RA);
106  riscv64cpu->SP = 0;
107  riscv64cpu->X[2] = & (riscv64cpu->SP);
108  riscv64cpu->GP = 0;
109  riscv64cpu->X[3] = & (riscv64cpu->GP);
110  riscv64cpu->TP = 0;
111  riscv64cpu->X[4] = & (riscv64cpu->TP);
112  riscv64cpu->T0 = 0;
113  riscv64cpu->X[5] = & (riscv64cpu->T0);
114  riscv64cpu->T1 = 0;
115  riscv64cpu->X[6] = & (riscv64cpu->T1);
116  riscv64cpu->T2 = 0;
117  riscv64cpu->X[7] = & (riscv64cpu->T2);
118  riscv64cpu->S0 = 0;
119  riscv64cpu->X[8] = & (riscv64cpu->S0);
120  riscv64cpu->S1 = 0;
121  riscv64cpu->X[9] = & (riscv64cpu->S1);
122  riscv64cpu->A0 = 0;
123  riscv64cpu->X[10] = & (riscv64cpu->A0);
124  riscv64cpu->A1 = 0;
125  riscv64cpu->X[11] = & (riscv64cpu->A1);
126  riscv64cpu->A2 = 0;
127  riscv64cpu->X[12] = & (riscv64cpu->A2);
128  riscv64cpu->A3 = 0;
129  riscv64cpu->X[13] = & (riscv64cpu->A3);
130  riscv64cpu->A4 = 0;
131  riscv64cpu->X[14] = & (riscv64cpu->A4);
132  riscv64cpu->A5 = 0;
133  riscv64cpu->X[15] = & (riscv64cpu->A5);
134  riscv64cpu->A6 = 0;
135  riscv64cpu->X[16] = & (riscv64cpu->A6);
136  riscv64cpu->A7 = 0;
137  riscv64cpu->X[17] = & (riscv64cpu->A7);
138  riscv64cpu->S2 = 0;
139  riscv64cpu->X[18] = & (riscv64cpu->S2);
140  riscv64cpu->S3 = 0;
141  riscv64cpu->X[19] = & (riscv64cpu->S3);
142  riscv64cpu->S4 = 0;
143  riscv64cpu->X[20] = & (riscv64cpu->S4);
144  riscv64cpu->S5 = 0;
145  riscv64cpu->X[21] = & (riscv64cpu->S5);
146  riscv64cpu->S6 = 0;
147  riscv64cpu->X[22] = & (riscv64cpu->S6);
148  riscv64cpu->S7 = 0;
149  riscv64cpu->X[23] = & (riscv64cpu->S7);
150  riscv64cpu->S8 = 0;
151  riscv64cpu->X[24] = & (riscv64cpu->S8);
152  riscv64cpu->S9 = 0;
153  riscv64cpu->X[25] = & (riscv64cpu->S9);
154  riscv64cpu->S10 = 0;
155  riscv64cpu->X[26] = & (riscv64cpu->S10);
156  riscv64cpu->S11 = 0;
157  riscv64cpu->X[27] = & (riscv64cpu->S11);
158  riscv64cpu->T3 = 0;
159  riscv64cpu->X[28] = & (riscv64cpu->T3);
160  riscv64cpu->T4 = 0;
161  riscv64cpu->X[29] = & (riscv64cpu->T4);
162  riscv64cpu->T5 = 0;
163  riscv64cpu->X[30] = & (riscv64cpu->T5);
164  riscv64cpu->T6 = 0;
165  riscv64cpu->X[31] = & (riscv64cpu->T6);
166  for (int i = 0; i<32 ;i++){
167  riscv64cpu->F[i] = 0;
168  }
169  riscv64cpu->FCSR = 0;
170  for (int i = 0; i<4096 ;i++){
171  riscv64cpu->CSR[i] = 0;
172  }
173  riscv64cpu->CSR[0] = 15;
174  riscv64cpu->CSR[256] = 15;
175  riscv64cpu->CSR[768] = 15;
176  riscv64cpu->CSR[260] = 4294967295;
177  riscv64cpu->CSR[769] = 1315077;
178  riscv64cpu->CSR[3088] = 3;
179  for (int i = 0; i<4 ;i++){
180  riscv64cpu->FENCE[i] = 0;
181  }
182  riscv64cpu->RES = 0;
183 
184  /* >>> manually added code section */
185  riscv64cpu->CSR[0x304] = (0xFFFFFFFFFFFFFBBB);
186  // MIE: enable all core-local and add. platform-specific interrupts
187  riscv64cpu->CSR[0x104] = riscv64cpu->CSR[0x304] & (~(0x888));
188  // SIE: enable all core-local and add. platform-specific interrupts (supervised)
189  riscv64cpu->CSR[0x004] = riscv64cpu->CSR[0x304] & (~(0xAAA));
190  // UIE: enable all core-local and add. platform-specific interrupts (user)
191  /* <<< manually added code section */
192 }
193 
194 void RISCV64Arch::deleteCPU(ETISS_CPU *cpu)
195 {
196  delete (RISCV64 *) cpu ;
197 }
198 
199 
203 unsigned RISCV64Arch::getMaximumInstructionSizeInBytes()
204 {
205  return 8;
206 }
210 unsigned RISCV64Arch::getInstructionSizeInBytes()
211 {
212  return 2;
213 }
217 const std::set<std::string> & RISCV64Arch::getHeaders() const
218 {
219  return headers_ ;
220 }
221 
222 void RISCV64Arch::initCodeBlock(etiss::CodeBlock & cb) const
223 {
224  cb.fileglobalCode().insert("#include \"Arch/RISCV64/RISCV64.h\"\n");
225 }
226 
227 etiss::plugin::gdb::GDBCore & RISCV64Arch::getGDBCore()
228 {
229 
230  return gdbcore_;
231 }
232 
233 // Manually added
234 etiss::Plugin *RISCV64Arch::newTimer(ETISS_CPU *cpu)
235 {
236  return (etiss::Plugin *)new RISCV64Timer();
237 }
238 
239 // Manually added
240 void RISCV64Arch::deleteTimer(etiss::Plugin *timer)
241 {
242  delete timer;
243 }
244 
245 // Manually added
246 etiss::mm::MMU *RISCV64Arch::newMMU(ETISS_CPU *cpu)
247 {
248  return (etiss::mm::MMU *)new RISCV64MMU(false);
249 }
250 
251 static const char * const reg_name[] =
252 {
253  "X0",
254  "X1",
255  "X2",
256  "X3",
257  "X4",
258  "X5",
259  "X6",
260  "X7",
261  "X8",
262  "X9",
263  "X10",
264  "X11",
265  "X12",
266  "X13",
267  "X14",
268  "X15",
269  "X16",
270  "X17",
271  "X18",
272  "X19",
273  "X20",
274  "X21",
275  "X22",
276  "X23",
277  "X24",
278  "X25",
279  "X26",
280  "X27",
281  "X28",
282  "X29",
283  "X30",
284  "X31",
285 };
286 
288 static InstructionDefinition lui_rd_imm(
289  ISA32_RISCV64,
290  "lui",
291  (uint32_t)0x37,
292  (uint32_t) 0x7f,
293  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
294  {
295  etiss_uint64 rd = 0;
296  static BitArrayRange R_rd_0 (11,7);
297  etiss_uint64 rd_0 = R_rd_0.read(ba);
298  rd += rd_0;
299  etiss_int64 imm = 0;
300  static BitArrayRange R_imm_12 (31,12);
301  etiss_int64 imm_12 = R_imm_12.read(ba);
302  imm += imm_12<<12;
303  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
304  partInit.getAffectedRegisters().add(reg_name[rd],64);
305  partInit.getAffectedRegisters().add("instructionPointer",64);
306  partInit.code() = std::string("//lui\n")+
307  "etiss_uint32 temp = 0;\n"
308  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
309  #if RISCV64_Pipeline1
310  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
311  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
312  "etiss_uint32 num_stages = 4;\n"
313  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
314  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
315  #endif
316  #if RISCV64_Pipeline2
317  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
318  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
319  "etiss_uint32 num_stages = 4;\n"
320  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
321  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
322  #endif
323 
324  "etiss_int64 imm_extended = 0;\n"
325 
326 "if((" + toString(imm) + " & 0x80000000)>>31 == 0)\n"
327 "{\n"
328  "imm_extended = 0;\n"
329  #if RISCV64_DEBUG_CALL
330  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
331  #endif
332 "}\n"
333 
334 "else\n"
335 "{\n"
336  "imm_extended = 4294967295;\n"
337  #if RISCV64_DEBUG_CALL
338  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
339  #endif
340  "imm_extended = (imm_extended << 32);\n"
341  #if RISCV64_DEBUG_CALL
342  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
343  #endif
344 "}\n"
345 "imm_extended = imm_extended + " + toString(imm) + ";\n"
346 #if RISCV64_DEBUG_CALL
347 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
348 #endif
349 "if(" + toString(rd) + " != 0)\n"
350 "{\n"
351  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = imm_extended;\n"
352  #if RISCV64_DEBUG_CALL
353  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
354  #endif
355 "}\n"
356 
357 
358  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
359 
360 ;
361 return true;
362 },
363 0,
364 nullptr
365 );
366 //-------------------------------------------------------------------------------------------------------------------
367 static InstructionDefinition auipc_rd_imm(
368  ISA32_RISCV64,
369  "auipc",
370  (uint32_t)0x17,
371  (uint32_t) 0x7f,
372  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
373  {
374  etiss_uint64 rd = 0;
375  static BitArrayRange R_rd_0 (11,7);
376  etiss_uint64 rd_0 = R_rd_0.read(ba);
377  rd += rd_0;
378  etiss_int64 imm = 0;
379  static BitArrayRange R_imm_12 (31,12);
380  etiss_int64 imm_12 = R_imm_12.read(ba);
381  imm += imm_12<<12;
382  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
383  partInit.getAffectedRegisters().add(reg_name[rd],64);
384  partInit.getAffectedRegisters().add("instructionPointer",64);
385  partInit.code() = std::string("//auipc\n")+
386  "etiss_uint32 temp = 0;\n"
387  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
388  #if RISCV64_Pipeline1
389  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
390  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
391  "etiss_uint32 num_stages = 4;\n"
392  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
393  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
394  #endif
395  #if RISCV64_Pipeline2
396  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
397  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
398  "etiss_uint32 num_stages = 4;\n"
399  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
400  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
401  #endif
402 
403  "etiss_int64 imm_extended = 0;\n"
404 
405 "if((" + toString(imm) + " & 0x80000000)>>31 == 0)\n"
406 "{\n"
407  "imm_extended = 0;\n"
408  #if RISCV64_DEBUG_CALL
409  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
410  #endif
411 "}\n"
412 
413 "else\n"
414 "{\n"
415  "imm_extended = 4294967295;\n"
416  #if RISCV64_DEBUG_CALL
417  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
418  #endif
419  "imm_extended = (imm_extended << 32);\n"
420  #if RISCV64_DEBUG_CALL
421  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
422  #endif
423 "}\n"
424 "imm_extended = imm_extended + " + toString(imm) + ";\n"
425 #if RISCV64_DEBUG_CALL
426 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
427 #endif
428 "if(" + toString(rd) + " != 0)\n"
429 "{\n"
430  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
431  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
432  "{\n"
433  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
434  "}\n"
435  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0 + imm_extended;\n"
436  #if RISCV64_DEBUG_CALL
437  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
438  #endif
439 "}\n"
440 
441 
442  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
443 
444 ;
445 return true;
446 },
447 0,
448 nullptr
449 );
450 //-------------------------------------------------------------------------------------------------------------------
451 static InstructionDefinition jal_rd_imm(
452  ISA32_RISCV64,
453  "jal",
454  (uint32_t)0x6f,
455  (uint32_t) 0x7f,
456  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
457  {
458  etiss_uint64 rd = 0;
459  static BitArrayRange R_rd_0 (11,7);
460  etiss_uint64 rd_0 = R_rd_0.read(ba);
461  rd += rd_0;
462  etiss_int64 imm = 0;
463  static BitArrayRange R_imm_20 (31,31);
464  etiss_int64 imm_20 = R_imm_20.read(ba);
465  imm += imm_20<<20;
466  static BitArrayRange R_imm_1 (30,21);
467  etiss_int64 imm_1 = R_imm_1.read(ba);
468  imm += imm_1<<1;
469  static BitArrayRange R_imm_11 (20,20);
470  etiss_int64 imm_11 = R_imm_11.read(ba);
471  imm += imm_11<<11;
472  static BitArrayRange R_imm_12 (19,12);
473  etiss_int64 imm_12 = R_imm_12.read(ba);
474  imm += imm_12<<12;
475  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
476  partInit.getAffectedRegisters().add(reg_name[rd],64);
477  partInit.getAffectedRegisters().add("instructionPointer",64);
478  partInit.code() = std::string("//jal\n")+
479  "etiss_uint32 temp = 0;\n"
480  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
481  #if RISCV64_Pipeline1
482  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
483  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
484  "etiss_uint32 num_stages = 4;\n"
485  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
486  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
487  #endif
488  #if RISCV64_Pipeline2
489  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
490  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
491  "etiss_uint32 num_stages = 4;\n"
492  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
493  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
494  #endif
495 
496  "etiss_int64 imm_extended = 0;\n"
497 
498 "if((" + toString(imm) + " & 0x100000)>>20 == 0)\n"
499 "{\n"
500  "imm_extended = 0;\n"
501  #if RISCV64_DEBUG_CALL
502  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
503  #endif
504 "}\n"
505 
506 "else\n"
507 "{\n"
508  "imm_extended = 4294967295;\n"
509  #if RISCV64_DEBUG_CALL
510  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
511  #endif
512  "imm_extended = (imm_extended << 32);\n"
513  #if RISCV64_DEBUG_CALL
514  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
515  #endif
516  "imm_extended = imm_extended + 4292870144;\n"
517  #if RISCV64_DEBUG_CALL
518  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
519  #endif
520 "}\n"
521 "imm_extended = imm_extended + " + toString(imm) + ";\n"
522 #if RISCV64_DEBUG_CALL
523 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
524 #endif
525 "if(" + toString(rd) + " != 0)\n"
526 "{\n"
527  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
528  #if RISCV64_DEBUG_CALL
529  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
530  #endif
531 "}\n"
532 
533 "else\n"
534 "{\n"
535 // Explicit assignment to PC
536 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
537 "}\n"
538 "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
539 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
540 "{\n"
541  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
542 "}\n"
543 "cpu->instructionPointer = (etiss_int64)cast_0 + imm_extended;\n"
544 #if RISCV64_DEBUG_CALL
545 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
546 #endif
547 
548  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
549 
550  "return 0;\n"
551 ;
552 return true;
553 },
554 0,
555 nullptr
556 );
557 //-------------------------------------------------------------------------------------------------------------------
558 static InstructionDefinition jalr_rd_rs1_imm(
559  ISA32_RISCV64,
560  "jalr",
561  (uint32_t)0x67,
562  (uint32_t) 0x707f,
563  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
564  {
565  etiss_uint64 rs1 = 0;
566  static BitArrayRange R_rs1_0 (19,15);
567  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
568  rs1 += rs1_0;
569  etiss_uint64 rd = 0;
570  static BitArrayRange R_rd_0 (11,7);
571  etiss_uint64 rd_0 = R_rd_0.read(ba);
572  rd += rd_0;
573  etiss_int64 imm = 0;
574  static BitArrayRange R_imm_0 (31,20);
575  etiss_int64 imm_0 = R_imm_0.read(ba);
576  imm += imm_0;
577  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
578  partInit.getRegisterDependencies().add(reg_name[rs1],64);
579  partInit.getAffectedRegisters().add(reg_name[rd],64);
580  partInit.getAffectedRegisters().add("instructionPointer",64);
581  partInit.code() = std::string("//jalr\n")+
582  "etiss_uint32 temp = 0;\n"
583  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
584  #if RISCV64_Pipeline1
585  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
586  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
587  "etiss_uint32 num_stages = 4;\n"
588  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
589  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
590  #endif
591  #if RISCV64_Pipeline2
592  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
593  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
594  "etiss_uint32 num_stages = 4;\n"
595  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
596  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
597  #endif
598 
599  "etiss_int64 imm_extended = 0;\n"
600  "etiss_int64 new_pc = 0;\n"
601 
602 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
603 "{\n"
604  "imm_extended = 0;\n"
605  #if RISCV64_DEBUG_CALL
606  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
607  #endif
608 "}\n"
609 
610 "else\n"
611 "{\n"
612  "imm_extended = 4294967295;\n"
613  #if RISCV64_DEBUG_CALL
614  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
615  #endif
616  "imm_extended = (imm_extended << 32);\n"
617  #if RISCV64_DEBUG_CALL
618  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
619  #endif
620  "imm_extended = imm_extended + 4294963200;\n"
621  #if RISCV64_DEBUG_CALL
622  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
623  #endif
624 "}\n"
625 "imm_extended = imm_extended + " + toString(imm) + ";\n"
626 #if RISCV64_DEBUG_CALL
627 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
628 #endif
629 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
630 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
631 "{\n"
632  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
633 "}\n"
634 "new_pc = (etiss_int64)cast_0 + imm_extended;\n"
635 #if RISCV64_DEBUG_CALL
636 "printf(\"new_pc = %#lx\\n\",new_pc); \n"
637 #endif
638 "if(" + toString(rd) + " != 0)\n"
639 "{\n"
640  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
641  #if RISCV64_DEBUG_CALL
642  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
643  #endif
644 "}\n"
645 
646 "else\n"
647 "{\n"
648 // Explicit assignment to PC
649 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
650 "}\n"
651 "cpu->instructionPointer = (new_pc & ~1)&0xffffffffffffffff;\n"
652 #if RISCV64_DEBUG_CALL
653 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
654 #endif
655 
656  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
657 
658  "return 0;\n"
659 ;
660 return true;
661 },
662 0,
663 nullptr
664 );
665 //-------------------------------------------------------------------------------------------------------------------
666 static InstructionDefinition beq_rs1_rs2_imm(
667  ISA32_RISCV64,
668  "beq",
669  (uint32_t)0x63,
670  (uint32_t) 0x707f,
671  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
672  {
673  etiss_uint64 rs2 = 0;
674  static BitArrayRange R_rs2_0 (24,20);
675  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
676  rs2 += rs2_0;
677  etiss_uint64 rs1 = 0;
678  static BitArrayRange R_rs1_0 (19,15);
679  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
680  rs1 += rs1_0;
681  etiss_int64 imm = 0;
682  static BitArrayRange R_imm_12 (31,31);
683  etiss_int64 imm_12 = R_imm_12.read(ba);
684  imm += imm_12<<12;
685  static BitArrayRange R_imm_5 (30,25);
686  etiss_int64 imm_5 = R_imm_5.read(ba);
687  imm += imm_5<<5;
688  static BitArrayRange R_imm_1 (11,8);
689  etiss_int64 imm_1 = R_imm_1.read(ba);
690  imm += imm_1<<1;
691  static BitArrayRange R_imm_11 (7,7);
692  etiss_int64 imm_11 = R_imm_11.read(ba);
693  imm += imm_11<<11;
694  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
695  partInit.getRegisterDependencies().add(reg_name[rs2],64);
696  partInit.getRegisterDependencies().add(reg_name[rs1],64);
697  partInit.getAffectedRegisters().add("instructionPointer",64);
698  partInit.code() = std::string("//beq\n")+
699  "etiss_uint32 temp = 0;\n"
700  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
701  #if RISCV64_Pipeline1
702  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
703  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
704  "etiss_uint32 num_stages = 4;\n"
705  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
706  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
707  #endif
708  #if RISCV64_Pipeline2
709  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
710  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
711  "etiss_uint32 num_stages = 4;\n"
712  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
713  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
714  #endif
715 
716  "etiss_int64 imm_extended = 0;\n"
717  "etiss_int64 choose1 = 0;\n"
718 
719 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
720 "{\n"
721  "imm_extended = 0;\n"
722  #if RISCV64_DEBUG_CALL
723  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
724  #endif
725 "}\n"
726 
727 "else\n"
728 "{\n"
729  "imm_extended = 4294967295;\n"
730  #if RISCV64_DEBUG_CALL
731  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
732  #endif
733  "imm_extended = (imm_extended << 32);\n"
734  #if RISCV64_DEBUG_CALL
735  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
736  #endif
737  "imm_extended = imm_extended + 4294959104;\n"
738  #if RISCV64_DEBUG_CALL
739  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
740  #endif
741 "}\n"
742 "imm_extended = imm_extended + " + toString(imm) + ";\n"
743 #if RISCV64_DEBUG_CALL
744 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
745 #endif
746 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + "] == *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
747 "{\n"
748  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
749  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
750  "{\n"
751  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
752  "}\n"
753  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
754  #if RISCV64_DEBUG_CALL
755  "printf(\"choose1 = %#lx\\n\",choose1); \n"
756  #endif
757 // Explicit assignment to PC
758 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
759 "}\n"
760 
761 "else\n"
762 "{\n"
763  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
764  #if RISCV64_DEBUG_CALL
765  "printf(\"choose1 = %#lx\\n\",choose1); \n"
766  #endif
767 "}\n"
768 "cpu->instructionPointer = choose1;\n"
769 #if RISCV64_DEBUG_CALL
770 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
771 #endif
772 
773  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
774 
775  "return 0;\n"
776 ;
777 return true;
778 },
779 0,
780 nullptr
781 );
782 //-------------------------------------------------------------------------------------------------------------------
783 static InstructionDefinition lb_rd_imm_rs1_(
784  ISA32_RISCV64,
785  "lb",
786  (uint32_t)0x3,
787  (uint32_t) 0x707f,
788  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
789  {
790  etiss_uint64 rs1 = 0;
791  static BitArrayRange R_rs1_0 (19,15);
792  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
793  rs1 += rs1_0;
794  etiss_uint64 rd = 0;
795  static BitArrayRange R_rd_0 (11,7);
796  etiss_uint64 rd_0 = R_rd_0.read(ba);
797  rd += rd_0;
798  etiss_int64 imm = 0;
799  static BitArrayRange R_imm_0 (31,20);
800  etiss_int64 imm_0 = R_imm_0.read(ba);
801  imm += imm_0;
802  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
803  partInit.getRegisterDependencies().add(reg_name[rs1],64);
804  partInit.getAffectedRegisters().add(reg_name[rd],64);
805  partInit.getAffectedRegisters().add("instructionPointer",64);
806  partInit.code() = std::string("//lb\n")+
807  "etiss_uint32 exception = 0;\n"
808  "etiss_uint32 temp = 0;\n"
809  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
810  #if RISCV64_Pipeline1
811  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
812  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
813  "etiss_uint32 num_stages = 4;\n"
814  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
815  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
816  #endif
817  #if RISCV64_Pipeline2
818  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
819  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
820  "etiss_uint32 num_stages = 4;\n"
821  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
822  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
823  #endif
824 
825  "etiss_int64 offs = 0;\n"
826  "etiss_int64 imm_extended = 0;\n"
827 
828 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
829 "{\n"
830  "imm_extended = 0;\n"
831  #if RISCV64_DEBUG_CALL
832  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
833  #endif
834 "}\n"
835 
836 "else\n"
837 "{\n"
838  "imm_extended = 4294967295;\n"
839  #if RISCV64_DEBUG_CALL
840  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
841  #endif
842  "imm_extended = (imm_extended << 32);\n"
843  #if RISCV64_DEBUG_CALL
844  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
845  #endif
846  "imm_extended = imm_extended + 4294963200;\n"
847  #if RISCV64_DEBUG_CALL
848  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
849  #endif
850 "}\n"
851 "imm_extended = imm_extended + " + toString(imm) + ";\n"
852 #if RISCV64_DEBUG_CALL
853 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
854 #endif
855 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
856 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
857 "{\n"
858  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
859 "}\n"
860 "offs = (etiss_int64)cast_0 + imm_extended;\n"
861 #if RISCV64_DEBUG_CALL
862 "printf(\"offs = %#lx\\n\",offs); \n"
863 #endif
864 "if(" + toString(rd) + " != 0)\n"
865 "{\n"
866  "etiss_uint8 MEM_offs;\n"
867  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
868  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,1);\n"
869  "etiss_int8 cast_1 = MEM_offs; \n"
870  "if((etiss_int8)((etiss_uint8)cast_1 - 0x80) > 0x0)\n"
871  "{\n"
872  "cast_1 =0x0 + (etiss_uint8)cast_1 ;\n"
873  "}\n"
874  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
875  #if RISCV64_DEBUG_CALL
876  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
877  #endif
878 "}\n"
879 
880 
881  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
882 
883  "return exception;\n"
884 ;
885 return true;
886 },
887 0,
888 nullptr
889 );
890 //-------------------------------------------------------------------------------------------------------------------
891 static InstructionDefinition sb_rs2_imm_rs1_(
892  ISA32_RISCV64,
893  "sb",
894  (uint32_t)0x23,
895  (uint32_t) 0x707f,
896  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
897  {
898  etiss_uint64 rs2 = 0;
899  static BitArrayRange R_rs2_0 (24,20);
900  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
901  rs2 += rs2_0;
902  etiss_uint64 rs1 = 0;
903  static BitArrayRange R_rs1_0 (19,15);
904  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
905  rs1 += rs1_0;
906  etiss_int64 imm = 0;
907  static BitArrayRange R_imm_5 (31,25);
908  etiss_int64 imm_5 = R_imm_5.read(ba);
909  imm += imm_5<<5;
910  static BitArrayRange R_imm_0 (11,7);
911  etiss_int64 imm_0 = R_imm_0.read(ba);
912  imm += imm_0;
913  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
914  partInit.getRegisterDependencies().add(reg_name[rs2],64);
915  partInit.getRegisterDependencies().add(reg_name[rs1],64);
916  partInit.getAffectedRegisters().add("instructionPointer",64);
917  partInit.code() = std::string("//sb\n")+
918  "etiss_uint32 exception = 0;\n"
919  "etiss_uint32 temp = 0;\n"
920  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
921  #if RISCV64_Pipeline1
922  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
923  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
924  "etiss_uint32 num_stages = 4;\n"
925  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
926  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
927  #endif
928  #if RISCV64_Pipeline2
929  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
930  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
931  "etiss_uint32 num_stages = 4;\n"
932  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
933  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
934  #endif
935 
936  "etiss_int64 offs = 0;\n"
937  "etiss_int64 imm_extended = 0;\n"
938 
939 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
940 "{\n"
941  "imm_extended = 0;\n"
942  #if RISCV64_DEBUG_CALL
943  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
944  #endif
945 "}\n"
946 
947 "else\n"
948 "{\n"
949  "imm_extended = 4294967295;\n"
950  #if RISCV64_DEBUG_CALL
951  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
952  #endif
953  "imm_extended = (imm_extended << 32);\n"
954  #if RISCV64_DEBUG_CALL
955  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
956  #endif
957  "imm_extended = imm_extended + 4294963200;\n"
958  #if RISCV64_DEBUG_CALL
959  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
960  #endif
961 "}\n"
962 "imm_extended = imm_extended + " + toString(imm) + ";\n"
963 #if RISCV64_DEBUG_CALL
964 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
965 #endif
966 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
967 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
968 "{\n"
969  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
970 "}\n"
971 "offs = (etiss_int64)cast_0 + imm_extended;\n"
972 #if RISCV64_DEBUG_CALL
973 "printf(\"offs = %#lx\\n\",offs); \n"
974 #endif
975  "etiss_uint8 MEM_offs;\n"
976 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
977 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
978 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,1);\n"
979 #if RISCV64_DEBUG_CALL
980 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
981 #endif
982 "if((offs + 1 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
983 "{\n"
984  "((RISCV64*)cpu)->RES = 0;\n"
985  #if RISCV64_DEBUG_CALL
986  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
987  #endif
988 "}\n"
989 
990 
991  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
992 
993  "return exception;\n"
994 ;
995 return true;
996 },
997 0,
998 nullptr
999 );
1000 //-------------------------------------------------------------------------------------------------------------------
1001 static InstructionDefinition addi_rd_rs1_imm(
1002  ISA32_RISCV64,
1003  "addi",
1004  (uint32_t)0x13,
1005  (uint32_t) 0x707f,
1006  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1007  {
1008  etiss_uint64 rs1 = 0;
1009  static BitArrayRange R_rs1_0 (19,15);
1010  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1011  rs1 += rs1_0;
1012  etiss_uint64 rd = 0;
1013  static BitArrayRange R_rd_0 (11,7);
1014  etiss_uint64 rd_0 = R_rd_0.read(ba);
1015  rd += rd_0;
1016  etiss_int64 imm = 0;
1017  static BitArrayRange R_imm_0 (31,20);
1018  etiss_int64 imm_0 = R_imm_0.read(ba);
1019  imm += imm_0;
1020  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1021  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1022  partInit.getAffectedRegisters().add(reg_name[rd],64);
1023  partInit.getAffectedRegisters().add("instructionPointer",64);
1024  partInit.code() = std::string("//addi\n")+
1025  "etiss_uint32 temp = 0;\n"
1026  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1027  #if RISCV64_Pipeline1
1028  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1029  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1030  "etiss_uint32 num_stages = 4;\n"
1031  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1032  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1033  #endif
1034  #if RISCV64_Pipeline2
1035  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1036  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1037  "etiss_uint32 num_stages = 4;\n"
1038  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1039  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1040  #endif
1041 
1042  "etiss_int64 imm_extended = 0;\n"
1043 
1044 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
1045 "{\n"
1046  "imm_extended = 0;\n"
1047  #if RISCV64_DEBUG_CALL
1048  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1049  #endif
1050 "}\n"
1051 
1052 "else\n"
1053 "{\n"
1054  "imm_extended = 4294967295;\n"
1055  #if RISCV64_DEBUG_CALL
1056  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1057  #endif
1058  "imm_extended = (imm_extended << 32);\n"
1059  #if RISCV64_DEBUG_CALL
1060  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1061  #endif
1062  "imm_extended = imm_extended + 4294963200;\n"
1063  #if RISCV64_DEBUG_CALL
1064  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1065  #endif
1066 "}\n"
1067 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1068 #if RISCV64_DEBUG_CALL
1069 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1070 #endif
1071 "if(" + toString(rd) + " != 0)\n"
1072 "{\n"
1073  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
1074  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1075  "{\n"
1076  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1077  "}\n"
1078  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0 + imm_extended;\n"
1079  #if RISCV64_DEBUG_CALL
1080  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
1081  #endif
1082 "}\n"
1083 
1084 
1085  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1086 
1087 ;
1088 return true;
1089 },
1090 0,
1091 nullptr
1092 );
1093 //-------------------------------------------------------------------------------------------------------------------
1094 static InstructionDefinition addiw_rd_rs1_imm(
1095  ISA32_RISCV64,
1096  "addiw",
1097  (uint32_t)0x1b,
1098  (uint32_t) 0x707f,
1099  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1100  {
1101  etiss_uint64 rs1 = 0;
1102  static BitArrayRange R_rs1_0 (19,15);
1103  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1104  rs1 += rs1_0;
1105  etiss_uint64 rd = 0;
1106  static BitArrayRange R_rd_0 (11,7);
1107  etiss_uint64 rd_0 = R_rd_0.read(ba);
1108  rd += rd_0;
1109  etiss_int64 imm = 0;
1110  static BitArrayRange R_imm_0 (31,20);
1111  etiss_int64 imm_0 = R_imm_0.read(ba);
1112  imm += imm_0;
1113  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1114  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1115  partInit.getAffectedRegisters().add(reg_name[rd],64);
1116  partInit.getAffectedRegisters().add("instructionPointer",64);
1117  partInit.code() = std::string("//addiw\n")+
1118  "etiss_uint32 temp = 0;\n"
1119  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1120  #if RISCV64_Pipeline1
1121  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1122  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1123  "etiss_uint32 num_stages = 4;\n"
1124  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1125  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1126  #endif
1127  #if RISCV64_Pipeline2
1128  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1129  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1130  "etiss_uint32 num_stages = 4;\n"
1131  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1132  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1133  #endif
1134 
1135  "etiss_int64 imm_extended = 0;\n"
1136  "etiss_int32 res = 0;\n"
1137 
1138 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
1139 "{\n"
1140  "imm_extended = 0;\n"
1141  #if RISCV64_DEBUG_CALL
1142  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1143  #endif
1144 "}\n"
1145 
1146 "else\n"
1147 "{\n"
1148  "imm_extended = 4294967295;\n"
1149  #if RISCV64_DEBUG_CALL
1150  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1151  #endif
1152  "imm_extended = (imm_extended << 32);\n"
1153  #if RISCV64_DEBUG_CALL
1154  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1155  #endif
1156  "imm_extended = imm_extended + 4294963200;\n"
1157  #if RISCV64_DEBUG_CALL
1158  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1159  #endif
1160 "}\n"
1161 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1162 #if RISCV64_DEBUG_CALL
1163 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1164 #endif
1165 "if(" + toString(rd) + " != 0)\n"
1166 "{\n"
1167  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
1168  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1169  "{\n"
1170  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1171  "}\n"
1172  "res = (etiss_int32)cast_0 + imm_extended;\n"
1173  #if RISCV64_DEBUG_CALL
1174  "printf(\"res = %#x\\n\",res); \n"
1175  #endif
1176  "etiss_int32 cast_1 = res; \n"
1177  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
1178  "{\n"
1179  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
1180  "}\n"
1181  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
1182  #if RISCV64_DEBUG_CALL
1183  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
1184  #endif
1185 "}\n"
1186 
1187 
1188  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1189 
1190 ;
1191 return true;
1192 },
1193 0,
1194 nullptr
1195 );
1196 //-------------------------------------------------------------------------------------------------------------------
1197 static InstructionDefinition bne_rs1_rs2_imm(
1198  ISA32_RISCV64,
1199  "bne",
1200  (uint32_t)0x1063,
1201  (uint32_t) 0x707f,
1202  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1203  {
1204  etiss_uint64 rs2 = 0;
1205  static BitArrayRange R_rs2_0 (24,20);
1206  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
1207  rs2 += rs2_0;
1208  etiss_uint64 rs1 = 0;
1209  static BitArrayRange R_rs1_0 (19,15);
1210  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1211  rs1 += rs1_0;
1212  etiss_int64 imm = 0;
1213  static BitArrayRange R_imm_12 (31,31);
1214  etiss_int64 imm_12 = R_imm_12.read(ba);
1215  imm += imm_12<<12;
1216  static BitArrayRange R_imm_5 (30,25);
1217  etiss_int64 imm_5 = R_imm_5.read(ba);
1218  imm += imm_5<<5;
1219  static BitArrayRange R_imm_1 (11,8);
1220  etiss_int64 imm_1 = R_imm_1.read(ba);
1221  imm += imm_1<<1;
1222  static BitArrayRange R_imm_11 (7,7);
1223  etiss_int64 imm_11 = R_imm_11.read(ba);
1224  imm += imm_11<<11;
1225  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1226  partInit.getRegisterDependencies().add(reg_name[rs2],64);
1227  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1228  partInit.getAffectedRegisters().add("instructionPointer",64);
1229  partInit.code() = std::string("//bne\n")+
1230  "etiss_uint32 temp = 0;\n"
1231  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1232  #if RISCV64_Pipeline1
1233  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1234  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1235  "etiss_uint32 num_stages = 4;\n"
1236  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1237  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1238  #endif
1239  #if RISCV64_Pipeline2
1240  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1241  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1242  "etiss_uint32 num_stages = 4;\n"
1243  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1244  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1245  #endif
1246 
1247  "etiss_int64 imm_extended = 0;\n"
1248  "etiss_int64 choose1 = 0;\n"
1249 
1250 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
1251 "{\n"
1252  "imm_extended = 0;\n"
1253  #if RISCV64_DEBUG_CALL
1254  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1255  #endif
1256 "}\n"
1257 
1258 "else\n"
1259 "{\n"
1260  "imm_extended = 4294967295;\n"
1261  #if RISCV64_DEBUG_CALL
1262  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1263  #endif
1264  "imm_extended = (imm_extended << 32);\n"
1265  #if RISCV64_DEBUG_CALL
1266  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1267  #endif
1268  "imm_extended = imm_extended + 4294959104;\n"
1269  #if RISCV64_DEBUG_CALL
1270  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1271  #endif
1272 "}\n"
1273 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1274 #if RISCV64_DEBUG_CALL
1275 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1276 #endif
1277 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + "] != *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
1278 "{\n"
1279  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
1280  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1281  "{\n"
1282  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1283  "}\n"
1284  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
1285  #if RISCV64_DEBUG_CALL
1286  "printf(\"choose1 = %#lx\\n\",choose1); \n"
1287  #endif
1288 // Explicit assignment to PC
1289 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1290 "}\n"
1291 
1292 "else\n"
1293 "{\n"
1294  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
1295  #if RISCV64_DEBUG_CALL
1296  "printf(\"choose1 = %#lx\\n\",choose1); \n"
1297  #endif
1298 "}\n"
1299 "cpu->instructionPointer = choose1;\n"
1300 #if RISCV64_DEBUG_CALL
1301 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
1302 #endif
1303 
1304  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
1305 
1306  "return 0;\n"
1307 ;
1308 return true;
1309 },
1310 0,
1311 nullptr
1312 );
1313 //-------------------------------------------------------------------------------------------------------------------
1314 static InstructionDefinition lh_rd_imm_rs1_(
1315  ISA32_RISCV64,
1316  "lh",
1317  (uint32_t)0x1003,
1318  (uint32_t) 0x707f,
1319  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1320  {
1321  etiss_uint64 rs1 = 0;
1322  static BitArrayRange R_rs1_0 (19,15);
1323  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1324  rs1 += rs1_0;
1325  etiss_uint64 rd = 0;
1326  static BitArrayRange R_rd_0 (11,7);
1327  etiss_uint64 rd_0 = R_rd_0.read(ba);
1328  rd += rd_0;
1329  etiss_int64 imm = 0;
1330  static BitArrayRange R_imm_0 (31,20);
1331  etiss_int64 imm_0 = R_imm_0.read(ba);
1332  imm += imm_0;
1333  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1334  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1335  partInit.getAffectedRegisters().add(reg_name[rd],64);
1336  partInit.getAffectedRegisters().add("instructionPointer",64);
1337  partInit.code() = std::string("//lh\n")+
1338  "etiss_uint32 exception = 0;\n"
1339  "etiss_uint32 temp = 0;\n"
1340  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1341  #if RISCV64_Pipeline1
1342  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1343  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1344  "etiss_uint32 num_stages = 4;\n"
1345  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1346  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1347  #endif
1348  #if RISCV64_Pipeline2
1349  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1350  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1351  "etiss_uint32 num_stages = 4;\n"
1352  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1353  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1354  #endif
1355 
1356  "etiss_int64 offs = 0;\n"
1357  "etiss_int64 imm_extended = 0;\n"
1358 
1359 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
1360 "{\n"
1361  "imm_extended = 0;\n"
1362  #if RISCV64_DEBUG_CALL
1363  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1364  #endif
1365 "}\n"
1366 
1367 "else\n"
1368 "{\n"
1369  "imm_extended = 4294967295;\n"
1370  #if RISCV64_DEBUG_CALL
1371  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1372  #endif
1373  "imm_extended = (imm_extended << 32);\n"
1374  #if RISCV64_DEBUG_CALL
1375  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1376  #endif
1377  "imm_extended = imm_extended + 4294963200;\n"
1378  #if RISCV64_DEBUG_CALL
1379  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1380  #endif
1381 "}\n"
1382 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1383 #if RISCV64_DEBUG_CALL
1384 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1385 #endif
1386 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
1387 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1388 "{\n"
1389  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1390 "}\n"
1391 "offs = (etiss_int64)cast_0 + imm_extended;\n"
1392 #if RISCV64_DEBUG_CALL
1393 "printf(\"offs = %#lx\\n\",offs); \n"
1394 #endif
1395 "if(" + toString(rd) + " != 0)\n"
1396 "{\n"
1397  "etiss_uint16 MEM_offs;\n"
1398  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
1399  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,2);\n"
1400  "etiss_int16 cast_1 = MEM_offs; \n"
1401  "if((etiss_int16)((etiss_uint16)cast_1 - 0x8000) > 0x0)\n"
1402  "{\n"
1403  "cast_1 =0x0 + (etiss_uint16)cast_1 ;\n"
1404  "}\n"
1405  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
1406  #if RISCV64_DEBUG_CALL
1407  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
1408  #endif
1409 "}\n"
1410 
1411 
1412  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1413 
1414  "return exception;\n"
1415 ;
1416 return true;
1417 },
1418 0,
1419 nullptr
1420 );
1421 //-------------------------------------------------------------------------------------------------------------------
1422 static InstructionDefinition sh_rs2_imm_rs1_(
1423  ISA32_RISCV64,
1424  "sh",
1425  (uint32_t)0x1023,
1426  (uint32_t) 0x707f,
1427  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1428  {
1429  etiss_uint64 rs2 = 0;
1430  static BitArrayRange R_rs2_0 (24,20);
1431  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
1432  rs2 += rs2_0;
1433  etiss_uint64 rs1 = 0;
1434  static BitArrayRange R_rs1_0 (19,15);
1435  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1436  rs1 += rs1_0;
1437  etiss_int64 imm = 0;
1438  static BitArrayRange R_imm_5 (31,25);
1439  etiss_int64 imm_5 = R_imm_5.read(ba);
1440  imm += imm_5<<5;
1441  static BitArrayRange R_imm_0 (11,7);
1442  etiss_int64 imm_0 = R_imm_0.read(ba);
1443  imm += imm_0;
1444  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1445  partInit.getRegisterDependencies().add(reg_name[rs2],64);
1446  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1447  partInit.getAffectedRegisters().add("instructionPointer",64);
1448  partInit.code() = std::string("//sh\n")+
1449  "etiss_uint32 exception = 0;\n"
1450  "etiss_uint32 temp = 0;\n"
1451  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1452  #if RISCV64_Pipeline1
1453  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1454  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1455  "etiss_uint32 num_stages = 4;\n"
1456  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1457  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1458  #endif
1459  #if RISCV64_Pipeline2
1460  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1461  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1462  "etiss_uint32 num_stages = 4;\n"
1463  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1464  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1465  #endif
1466 
1467  "etiss_int64 offs = 0;\n"
1468  "etiss_int64 imm_extended = 0;\n"
1469 
1470 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
1471 "{\n"
1472  "imm_extended = 0;\n"
1473  #if RISCV64_DEBUG_CALL
1474  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1475  #endif
1476 "}\n"
1477 
1478 "else\n"
1479 "{\n"
1480  "imm_extended = 4294967295;\n"
1481  #if RISCV64_DEBUG_CALL
1482  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1483  #endif
1484  "imm_extended = (imm_extended << 32);\n"
1485  #if RISCV64_DEBUG_CALL
1486  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1487  #endif
1488  "imm_extended = imm_extended + 4294963200;\n"
1489  #if RISCV64_DEBUG_CALL
1490  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1491  #endif
1492 "}\n"
1493 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1494 #if RISCV64_DEBUG_CALL
1495 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1496 #endif
1497 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
1498 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1499 "{\n"
1500  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1501 "}\n"
1502 "offs = (etiss_int64)cast_0 + imm_extended;\n"
1503 #if RISCV64_DEBUG_CALL
1504 "printf(\"offs = %#lx\\n\",offs); \n"
1505 #endif
1506  "etiss_uint16 MEM_offs;\n"
1507 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
1508 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
1509 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,2);\n"
1510 #if RISCV64_DEBUG_CALL
1511 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
1512 #endif
1513 "if((offs + 2 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
1514 "{\n"
1515  "((RISCV64*)cpu)->RES = 0;\n"
1516  #if RISCV64_DEBUG_CALL
1517  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
1518  #endif
1519 "}\n"
1520 
1521 
1522  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1523 
1524  "return exception;\n"
1525 ;
1526 return true;
1527 },
1528 0,
1529 nullptr
1530 );
1531 //-------------------------------------------------------------------------------------------------------------------
1532 static InstructionDefinition fence_i_(
1533  ISA32_RISCV64,
1534  "fence_i",
1535  (uint32_t)0x100f,
1536  (uint32_t) 0x707f,
1537  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1538  {
1539  etiss_uint64 rs1 = 0;
1540  static BitArrayRange R_rs1_0 (19,15);
1541  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1542  rs1 += rs1_0;
1543  etiss_uint64 rd = 0;
1544  static BitArrayRange R_rd_0 (11,7);
1545  etiss_uint64 rd_0 = R_rd_0.read(ba);
1546  rd += rd_0;
1547  etiss_uint64 imm = 0;
1548  static BitArrayRange R_imm_0 (31,20);
1549  etiss_uint64 imm_0 = R_imm_0.read(ba);
1550  imm += imm_0;
1551  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1552  partInit.getAffectedRegisters().add(reg_name[1],64);
1553  partInit.getAffectedRegisters().add("instructionPointer",64);
1554  partInit.code() = std::string("//fence_i\n")+
1555  "etiss_uint32 temp = 0;\n"
1556  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1557  #if RISCV64_Pipeline1
1558  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1559  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1560  "etiss_uint32 num_stages = 4;\n"
1561  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1562  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1563  #endif
1564  #if RISCV64_Pipeline2
1565  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1566  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1567  "etiss_uint32 num_stages = 4;\n"
1568  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1569  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1570  #endif
1571 
1572 
1573 "((RISCV64*)cpu)->FENCE[1] = " + toString(imm) + ";\n"
1574 #if RISCV64_DEBUG_CALL
1575 "printf(\"((RISCV64*)cpu)->FENCE[1] = %#lx\\n\",((RISCV64*)cpu)->FENCE[1]); \n"
1576 #endif
1577 
1578  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1579 
1580 ;
1581 return true;
1582 },
1583 0,
1584 nullptr
1585 );
1586 //-------------------------------------------------------------------------------------------------------------------
1587 static InstructionDefinition csrrw_rd_csr_rs1(
1588  ISA32_RISCV64,
1589  "csrrw",
1590  (uint32_t)0x1073,
1591  (uint32_t) 0x707f,
1592  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1593  {
1594  etiss_uint64 rs1 = 0;
1595  static BitArrayRange R_rs1_0 (19,15);
1596  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1597  rs1 += rs1_0;
1598  etiss_uint64 rd = 0;
1599  static BitArrayRange R_rd_0 (11,7);
1600  etiss_uint64 rd_0 = R_rd_0.read(ba);
1601  rd += rd_0;
1602  etiss_uint64 csr = 0;
1603  static BitArrayRange R_csr_0 (31,20);
1604  etiss_uint64 csr_0 = R_csr_0.read(ba);
1605  csr += csr_0;
1606  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1607  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1608  partInit.getAffectedRegisters().add(reg_name[rd],64);
1609  partInit.getAffectedRegisters().add("instructionPointer",64);
1610  partInit.code() = std::string("//csrrw\n")+
1611  "etiss_uint32 temp = 0;\n"
1612  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1613  #if RISCV64_Pipeline1
1614  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1615  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1616  "etiss_uint32 num_stages = 4;\n"
1617  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1618  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1619  #endif
1620  #if RISCV64_Pipeline2
1621  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1622  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1623  "etiss_uint32 num_stages = 4;\n"
1624  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1625  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1626  #endif
1627 
1628  "etiss_int64 mAddr = 0;\n"
1629  "etiss_int64 writeMask = 0;\n"
1630  "etiss_int64 writeMaskU = 0;\n"
1631  "etiss_int64 sAddr = 0;\n"
1632  "etiss_int64 writeMaskS = 0;\n"
1633  "etiss_int64 uAddr = 0;\n"
1634  "etiss_uint64 rs_val = 0;\n"
1635  "etiss_uint64 csr_val = 0;\n"
1636  "etiss_int64 writeMaskM = 0;\n"
1637 
1638 "rs_val = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
1639 #if RISCV64_DEBUG_CALL
1640 "printf(\"rs_val = %#lx\\n\",rs_val); \n"
1641 #endif
1642 "if(" + toString(rd) + " != 0)\n"
1643 "{\n"
1644  "csr_val = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
1645  #if RISCV64_DEBUG_CALL
1646  "printf(\"csr_val = %#lx\\n\",csr_val); \n"
1647  #endif
1648  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
1649  "{\n"
1650  "uAddr = 0;\n"
1651  #if RISCV64_DEBUG_CALL
1652  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1653  #endif
1654  "sAddr = 256;\n"
1655  #if RISCV64_DEBUG_CALL
1656  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1657  #endif
1658  "mAddr = 768;\n"
1659  #if RISCV64_DEBUG_CALL
1660  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1661  #endif
1662  "writeMaskM = -9223372036846388805;\n"
1663  #if RISCV64_DEBUG_CALL
1664  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1665  #endif
1666  "writeMaskS = -9223372036853866189;\n"
1667  #if RISCV64_DEBUG_CALL
1668  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1669  #endif
1670  "writeMaskU = -9223372036853866479;\n"
1671  #if RISCV64_DEBUG_CALL
1672  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1673  #endif
1674  "}\n"
1675 
1676  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
1677  "{\n"
1678  "uAddr = 68;\n"
1679  #if RISCV64_DEBUG_CALL
1680  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1681  #endif
1682  "sAddr = 324;\n"
1683  #if RISCV64_DEBUG_CALL
1684  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1685  #endif
1686  "mAddr = 836;\n"
1687  #if RISCV64_DEBUG_CALL
1688  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1689  #endif
1690  "writeMaskM = 3003;\n"
1691  #if RISCV64_DEBUG_CALL
1692  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1693  #endif
1694  "writeMaskS = 819;\n"
1695  #if RISCV64_DEBUG_CALL
1696  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1697  #endif
1698  "writeMaskU = 273;\n"
1699  #if RISCV64_DEBUG_CALL
1700  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1701  #endif
1702  "}\n"
1703 
1704  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
1705  "{\n"
1706  "uAddr = 4;\n"
1707  #if RISCV64_DEBUG_CALL
1708  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1709  #endif
1710  "sAddr = 260;\n"
1711  #if RISCV64_DEBUG_CALL
1712  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1713  #endif
1714  "mAddr = 772;\n"
1715  #if RISCV64_DEBUG_CALL
1716  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1717  #endif
1718  "writeMaskM = 3003;\n"
1719  #if RISCV64_DEBUG_CALL
1720  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1721  #endif
1722  "writeMaskS = 819;\n"
1723  #if RISCV64_DEBUG_CALL
1724  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1725  #endif
1726  "writeMaskU = 273;\n"
1727  #if RISCV64_DEBUG_CALL
1728  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1729  #endif
1730  "}\n"
1731 
1732  "if(uAddr != sAddr)\n"
1733  "{\n"
1734  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
1735  "{\n"
1736  "writeMask = writeMaskM;\n"
1737  #if RISCV64_DEBUG_CALL
1738  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1739  #endif
1740  "}\n"
1741 
1742  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
1743  "{\n"
1744  "writeMask = writeMaskS;\n"
1745  #if RISCV64_DEBUG_CALL
1746  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1747  #endif
1748  "}\n"
1749 
1750  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
1751  "{\n"
1752  "writeMask = writeMaskU;\n"
1753  #if RISCV64_DEBUG_CALL
1754  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1755  #endif
1756  "}\n"
1757 
1758  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffffffffffff;\n"
1759  #if RISCV64_DEBUG_CALL
1760  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
1761  #endif
1762  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
1763  #if RISCV64_DEBUG_CALL
1764  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
1765  #endif
1766  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
1767  #if RISCV64_DEBUG_CALL
1768  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
1769  #endif
1770  "}\n"
1771 
1772  "else\n"
1773  "{\n"
1774  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = rs_val;\n"
1775  #if RISCV64_DEBUG_CALL
1776  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
1777  #endif
1778  "}\n"
1779  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = csr_val;\n"
1780  #if RISCV64_DEBUG_CALL
1781  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
1782  #endif
1783 "}\n"
1784 
1785 "else\n"
1786 "{\n"
1787  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
1788  "{\n"
1789  "uAddr = 0;\n"
1790  #if RISCV64_DEBUG_CALL
1791  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1792  #endif
1793  "sAddr = 256;\n"
1794  #if RISCV64_DEBUG_CALL
1795  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1796  #endif
1797  "mAddr = 768;\n"
1798  #if RISCV64_DEBUG_CALL
1799  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1800  #endif
1801  "writeMaskM = -9223372036846388805;\n"
1802  #if RISCV64_DEBUG_CALL
1803  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1804  #endif
1805  "writeMaskS = -9223372036853866189;\n"
1806  #if RISCV64_DEBUG_CALL
1807  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1808  #endif
1809  "writeMaskU = -9223372036853866479;\n"
1810  #if RISCV64_DEBUG_CALL
1811  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1812  #endif
1813  "}\n"
1814 
1815  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
1816  "{\n"
1817  "uAddr = 68;\n"
1818  #if RISCV64_DEBUG_CALL
1819  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1820  #endif
1821  "sAddr = 324;\n"
1822  #if RISCV64_DEBUG_CALL
1823  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1824  #endif
1825  "mAddr = 836;\n"
1826  #if RISCV64_DEBUG_CALL
1827  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1828  #endif
1829  "writeMaskM = 3003;\n"
1830  #if RISCV64_DEBUG_CALL
1831  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1832  #endif
1833  "writeMaskS = 819;\n"
1834  #if RISCV64_DEBUG_CALL
1835  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1836  #endif
1837  "writeMaskU = 273;\n"
1838  #if RISCV64_DEBUG_CALL
1839  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1840  #endif
1841  "}\n"
1842 
1843  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
1844  "{\n"
1845  "uAddr = 4;\n"
1846  #if RISCV64_DEBUG_CALL
1847  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1848  #endif
1849  "sAddr = 260;\n"
1850  #if RISCV64_DEBUG_CALL
1851  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1852  #endif
1853  "mAddr = 772;\n"
1854  #if RISCV64_DEBUG_CALL
1855  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1856  #endif
1857  "writeMaskM = 3003;\n"
1858  #if RISCV64_DEBUG_CALL
1859  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1860  #endif
1861  "writeMaskS = 819;\n"
1862  #if RISCV64_DEBUG_CALL
1863  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1864  #endif
1865  "writeMaskU = 273;\n"
1866  #if RISCV64_DEBUG_CALL
1867  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1868  #endif
1869  "}\n"
1870 
1871  "if(uAddr != sAddr)\n"
1872  "{\n"
1873  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
1874  "{\n"
1875  "writeMask = writeMaskM;\n"
1876  #if RISCV64_DEBUG_CALL
1877  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1878  #endif
1879  "}\n"
1880 
1881  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
1882  "{\n"
1883  "writeMask = writeMaskS;\n"
1884  #if RISCV64_DEBUG_CALL
1885  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1886  #endif
1887  "}\n"
1888 
1889  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
1890  "{\n"
1891  "writeMask = writeMaskU;\n"
1892  #if RISCV64_DEBUG_CALL
1893  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1894  #endif
1895  "}\n"
1896 
1897  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffffffffffff;\n"
1898  #if RISCV64_DEBUG_CALL
1899  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
1900  #endif
1901  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
1902  #if RISCV64_DEBUG_CALL
1903  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
1904  #endif
1905  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
1906  #if RISCV64_DEBUG_CALL
1907  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
1908  #endif
1909  "}\n"
1910 
1911  "else\n"
1912  "{\n"
1913  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = rs_val;\n"
1914  #if RISCV64_DEBUG_CALL
1915  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
1916  #endif
1917  "}\n"
1918 "}\n"
1919 
1920  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1921 
1922 ;
1923 return true;
1924 },
1925 0,
1926 nullptr
1927 );
1928 //-------------------------------------------------------------------------------------------------------------------
1929 static InstructionDefinition blt_rs1_rs2_imm(
1930  ISA32_RISCV64,
1931  "blt",
1932  (uint32_t)0x4063,
1933  (uint32_t) 0x707f,
1934  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1935  {
1936  etiss_uint64 rs2 = 0;
1937  static BitArrayRange R_rs2_0 (24,20);
1938  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
1939  rs2 += rs2_0;
1940  etiss_uint64 rs1 = 0;
1941  static BitArrayRange R_rs1_0 (19,15);
1942  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1943  rs1 += rs1_0;
1944  etiss_int64 imm = 0;
1945  static BitArrayRange R_imm_12 (31,31);
1946  etiss_int64 imm_12 = R_imm_12.read(ba);
1947  imm += imm_12<<12;
1948  static BitArrayRange R_imm_5 (30,25);
1949  etiss_int64 imm_5 = R_imm_5.read(ba);
1950  imm += imm_5<<5;
1951  static BitArrayRange R_imm_1 (11,8);
1952  etiss_int64 imm_1 = R_imm_1.read(ba);
1953  imm += imm_1<<1;
1954  static BitArrayRange R_imm_11 (7,7);
1955  etiss_int64 imm_11 = R_imm_11.read(ba);
1956  imm += imm_11<<11;
1957  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1958  partInit.getRegisterDependencies().add(reg_name[rs2],64);
1959  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1960  partInit.getAffectedRegisters().add("instructionPointer",64);
1961  partInit.code() = std::string("//blt\n")+
1962  "etiss_uint32 temp = 0;\n"
1963  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1964  #if RISCV64_Pipeline1
1965  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1966  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1967  "etiss_uint32 num_stages = 4;\n"
1968  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1969  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1970  #endif
1971  #if RISCV64_Pipeline2
1972  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1973  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1974  "etiss_uint32 num_stages = 4;\n"
1975  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1976  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1977  #endif
1978 
1979  "etiss_int64 imm_extended = 0;\n"
1980  "etiss_int64 choose1 = 0;\n"
1981 
1982 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
1983 "{\n"
1984  "imm_extended = 0;\n"
1985  #if RISCV64_DEBUG_CALL
1986  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1987  #endif
1988 "}\n"
1989 
1990 "else\n"
1991 "{\n"
1992  "imm_extended = 4294967295;\n"
1993  #if RISCV64_DEBUG_CALL
1994  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1995  #endif
1996  "imm_extended = (imm_extended << 32);\n"
1997  #if RISCV64_DEBUG_CALL
1998  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1999  #endif
2000  "imm_extended = imm_extended + 4294959104;\n"
2001  #if RISCV64_DEBUG_CALL
2002  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2003  #endif
2004 "}\n"
2005 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2006 #if RISCV64_DEBUG_CALL
2007 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2008 #endif
2009 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
2010 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2011 "{\n"
2012  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2013 "}\n"
2014 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2015 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
2016 "{\n"
2017  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
2018 "}\n"
2019 "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n"
2020 "{\n"
2021  "etiss_int64 cast_2 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
2022  "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
2023  "{\n"
2024  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
2025  "}\n"
2026  "choose1 = (etiss_int64)cast_2 + imm_extended;\n"
2027  #if RISCV64_DEBUG_CALL
2028  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2029  #endif
2030 // Explicit assignment to PC
2031 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2032 "}\n"
2033 
2034 "else\n"
2035 "{\n"
2036  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
2037  #if RISCV64_DEBUG_CALL
2038  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2039  #endif
2040 "}\n"
2041 "cpu->instructionPointer = choose1;\n"
2042 #if RISCV64_DEBUG_CALL
2043 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
2044 #endif
2045 
2046  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
2047 
2048  "return 0;\n"
2049 ;
2050 return true;
2051 },
2052 0,
2053 nullptr
2054 );
2055 //-------------------------------------------------------------------------------------------------------------------
2056 static InstructionDefinition lbu_rd_imm_rs1_(
2057  ISA32_RISCV64,
2058  "lbu",
2059  (uint32_t)0x4003,
2060  (uint32_t) 0x707f,
2061  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2062  {
2063  etiss_uint64 rs1 = 0;
2064  static BitArrayRange R_rs1_0 (19,15);
2065  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2066  rs1 += rs1_0;
2067  etiss_uint64 rd = 0;
2068  static BitArrayRange R_rd_0 (11,7);
2069  etiss_uint64 rd_0 = R_rd_0.read(ba);
2070  rd += rd_0;
2071  etiss_int64 imm = 0;
2072  static BitArrayRange R_imm_0 (31,20);
2073  etiss_int64 imm_0 = R_imm_0.read(ba);
2074  imm += imm_0;
2075  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2076  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2077  partInit.getAffectedRegisters().add(reg_name[rd],64);
2078  partInit.getAffectedRegisters().add("instructionPointer",64);
2079  partInit.code() = std::string("//lbu\n")+
2080  "etiss_uint32 exception = 0;\n"
2081  "etiss_uint32 temp = 0;\n"
2082  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2083  #if RISCV64_Pipeline1
2084  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2085  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2086  "etiss_uint32 num_stages = 4;\n"
2087  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2088  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2089  #endif
2090  #if RISCV64_Pipeline2
2091  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2092  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2093  "etiss_uint32 num_stages = 4;\n"
2094  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2095  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2096  #endif
2097 
2098  "etiss_int64 offs = 0;\n"
2099  "etiss_int64 imm_extended = 0;\n"
2100 
2101 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
2102 "{\n"
2103  "imm_extended = 0;\n"
2104  #if RISCV64_DEBUG_CALL
2105  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2106  #endif
2107 "}\n"
2108 
2109 "else\n"
2110 "{\n"
2111  "imm_extended = 4294967295;\n"
2112  #if RISCV64_DEBUG_CALL
2113  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2114  #endif
2115  "imm_extended = (imm_extended << 32);\n"
2116  #if RISCV64_DEBUG_CALL
2117  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2118  #endif
2119  "imm_extended = imm_extended + 4294963200;\n"
2120  #if RISCV64_DEBUG_CALL
2121  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2122  #endif
2123 "}\n"
2124 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2125 #if RISCV64_DEBUG_CALL
2126 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2127 #endif
2128 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2129 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2130 "{\n"
2131  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2132 "}\n"
2133 "offs = (etiss_int64)cast_0 + imm_extended;\n"
2134 #if RISCV64_DEBUG_CALL
2135 "printf(\"offs = %#lx\\n\",offs); \n"
2136 #endif
2137 "if(" + toString(rd) + " != 0)\n"
2138 "{\n"
2139  "etiss_uint8 MEM_offs;\n"
2140  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
2141  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,1);\n"
2142  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)MEM_offs;\n"
2143  #if RISCV64_DEBUG_CALL
2144  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2145  #endif
2146 "}\n"
2147 
2148 
2149  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2150 
2151  "return exception;\n"
2152 ;
2153 return true;
2154 },
2155 0,
2156 nullptr
2157 );
2158 //-------------------------------------------------------------------------------------------------------------------
2159 static InstructionDefinition xori_rd_rs1_imm(
2160  ISA32_RISCV64,
2161  "xori",
2162  (uint32_t)0x4013,
2163  (uint32_t) 0x707f,
2164  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2165  {
2166  etiss_uint64 rs1 = 0;
2167  static BitArrayRange R_rs1_0 (19,15);
2168  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2169  rs1 += rs1_0;
2170  etiss_uint64 rd = 0;
2171  static BitArrayRange R_rd_0 (11,7);
2172  etiss_uint64 rd_0 = R_rd_0.read(ba);
2173  rd += rd_0;
2174  etiss_int64 imm = 0;
2175  static BitArrayRange R_imm_0 (31,20);
2176  etiss_int64 imm_0 = R_imm_0.read(ba);
2177  imm += imm_0;
2178  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2179  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2180  partInit.getAffectedRegisters().add(reg_name[rd],64);
2181  partInit.getAffectedRegisters().add("instructionPointer",64);
2182  partInit.code() = std::string("//xori\n")+
2183  "etiss_uint32 temp = 0;\n"
2184  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2185  #if RISCV64_Pipeline1
2186  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2187  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2188  "etiss_uint32 num_stages = 4;\n"
2189  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2190  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2191  #endif
2192  #if RISCV64_Pipeline2
2193  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2194  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2195  "etiss_uint32 num_stages = 4;\n"
2196  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2197  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2198  #endif
2199 
2200  "etiss_int64 imm_extended = 0;\n"
2201 
2202 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
2203 "{\n"
2204  "imm_extended = 0;\n"
2205  #if RISCV64_DEBUG_CALL
2206  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2207  #endif
2208 "}\n"
2209 
2210 "else\n"
2211 "{\n"
2212  "imm_extended = 4294967295;\n"
2213  #if RISCV64_DEBUG_CALL
2214  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2215  #endif
2216  "imm_extended = (imm_extended << 32);\n"
2217  #if RISCV64_DEBUG_CALL
2218  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2219  #endif
2220  "imm_extended = imm_extended + 4294963200;\n"
2221  #if RISCV64_DEBUG_CALL
2222  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2223  #endif
2224 "}\n"
2225 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2226 #if RISCV64_DEBUG_CALL
2227 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2228 #endif
2229 "if(" + toString(rd) + " != 0)\n"
2230 "{\n"
2231  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2232  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2233  "{\n"
2234  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2235  "}\n"
2236  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 ^ imm_extended);\n"
2237  #if RISCV64_DEBUG_CALL
2238  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2239  #endif
2240 "}\n"
2241 
2242 
2243  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2244 
2245 ;
2246 return true;
2247 },
2248 0,
2249 nullptr
2250 );
2251 //-------------------------------------------------------------------------------------------------------------------
2252 static InstructionDefinition bge_rs1_rs2_imm(
2253  ISA32_RISCV64,
2254  "bge",
2255  (uint32_t)0x5063,
2256  (uint32_t) 0x707f,
2257  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2258  {
2259  etiss_uint64 rs2 = 0;
2260  static BitArrayRange R_rs2_0 (24,20);
2261  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
2262  rs2 += rs2_0;
2263  etiss_uint64 rs1 = 0;
2264  static BitArrayRange R_rs1_0 (19,15);
2265  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2266  rs1 += rs1_0;
2267  etiss_int64 imm = 0;
2268  static BitArrayRange R_imm_12 (31,31);
2269  etiss_int64 imm_12 = R_imm_12.read(ba);
2270  imm += imm_12<<12;
2271  static BitArrayRange R_imm_5 (30,25);
2272  etiss_int64 imm_5 = R_imm_5.read(ba);
2273  imm += imm_5<<5;
2274  static BitArrayRange R_imm_1 (11,8);
2275  etiss_int64 imm_1 = R_imm_1.read(ba);
2276  imm += imm_1<<1;
2277  static BitArrayRange R_imm_11 (7,7);
2278  etiss_int64 imm_11 = R_imm_11.read(ba);
2279  imm += imm_11<<11;
2280  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2281  partInit.getRegisterDependencies().add(reg_name[rs2],64);
2282  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2283  partInit.getAffectedRegisters().add("instructionPointer",64);
2284  partInit.code() = std::string("//bge\n")+
2285  "etiss_uint32 temp = 0;\n"
2286  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2287  #if RISCV64_Pipeline1
2288  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2289  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2290  "etiss_uint32 num_stages = 4;\n"
2291  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2292  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2293  #endif
2294  #if RISCV64_Pipeline2
2295  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2296  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2297  "etiss_uint32 num_stages = 4;\n"
2298  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2299  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2300  #endif
2301 
2302  "etiss_int64 imm_extended = 0;\n"
2303  "etiss_int64 choose1 = 0;\n"
2304 
2305 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
2306 "{\n"
2307  "imm_extended = 0;\n"
2308  #if RISCV64_DEBUG_CALL
2309  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2310  #endif
2311 "}\n"
2312 
2313 "else\n"
2314 "{\n"
2315  "imm_extended = 4294967295;\n"
2316  #if RISCV64_DEBUG_CALL
2317  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2318  #endif
2319  "imm_extended = (imm_extended << 32);\n"
2320  #if RISCV64_DEBUG_CALL
2321  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2322  #endif
2323  "imm_extended = imm_extended + 4294959104;\n"
2324  #if RISCV64_DEBUG_CALL
2325  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2326  #endif
2327 "}\n"
2328 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2329 #if RISCV64_DEBUG_CALL
2330 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2331 #endif
2332 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
2333 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2334 "{\n"
2335  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2336 "}\n"
2337 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2338 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
2339 "{\n"
2340  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
2341 "}\n"
2342 "if((etiss_int64)cast_1 >= (etiss_int64)cast_0)\n"
2343 "{\n"
2344  "etiss_int64 cast_2 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
2345  "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
2346  "{\n"
2347  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
2348  "}\n"
2349  "choose1 = (etiss_int64)cast_2 + imm_extended;\n"
2350  #if RISCV64_DEBUG_CALL
2351  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2352  #endif
2353 // Explicit assignment to PC
2354 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2355 "}\n"
2356 
2357 "else\n"
2358 "{\n"
2359  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
2360  #if RISCV64_DEBUG_CALL
2361  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2362  #endif
2363 "}\n"
2364 "cpu->instructionPointer = choose1;\n"
2365 #if RISCV64_DEBUG_CALL
2366 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
2367 #endif
2368 
2369  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
2370 
2371  "return 0;\n"
2372 ;
2373 return true;
2374 },
2375 0,
2376 nullptr
2377 );
2378 //-------------------------------------------------------------------------------------------------------------------
2379 static InstructionDefinition lhu_rd_imm_rs1_(
2380  ISA32_RISCV64,
2381  "lhu",
2382  (uint32_t)0x5003,
2383  (uint32_t) 0x707f,
2384  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2385  {
2386  etiss_uint64 rs1 = 0;
2387  static BitArrayRange R_rs1_0 (19,15);
2388  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2389  rs1 += rs1_0;
2390  etiss_uint64 rd = 0;
2391  static BitArrayRange R_rd_0 (11,7);
2392  etiss_uint64 rd_0 = R_rd_0.read(ba);
2393  rd += rd_0;
2394  etiss_int64 imm = 0;
2395  static BitArrayRange R_imm_0 (31,20);
2396  etiss_int64 imm_0 = R_imm_0.read(ba);
2397  imm += imm_0;
2398  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2399  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2400  partInit.getAffectedRegisters().add(reg_name[rd],64);
2401  partInit.getAffectedRegisters().add("instructionPointer",64);
2402  partInit.code() = std::string("//lhu\n")+
2403  "etiss_uint32 exception = 0;\n"
2404  "etiss_uint32 temp = 0;\n"
2405  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2406  #if RISCV64_Pipeline1
2407  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2408  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2409  "etiss_uint32 num_stages = 4;\n"
2410  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2411  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2412  #endif
2413  #if RISCV64_Pipeline2
2414  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2415  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2416  "etiss_uint32 num_stages = 4;\n"
2417  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2418  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2419  #endif
2420 
2421  "etiss_int64 offs = 0;\n"
2422  "etiss_int64 imm_extended = 0;\n"
2423 
2424 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
2425 "{\n"
2426  "imm_extended = 0;\n"
2427  #if RISCV64_DEBUG_CALL
2428  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2429  #endif
2430 "}\n"
2431 
2432 "else\n"
2433 "{\n"
2434  "imm_extended = 4294967295;\n"
2435  #if RISCV64_DEBUG_CALL
2436  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2437  #endif
2438  "imm_extended = (imm_extended << 32);\n"
2439  #if RISCV64_DEBUG_CALL
2440  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2441  #endif
2442  "imm_extended = imm_extended + 4294963200;\n"
2443  #if RISCV64_DEBUG_CALL
2444  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2445  #endif
2446 "}\n"
2447 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2448 #if RISCV64_DEBUG_CALL
2449 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2450 #endif
2451 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2452 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2453 "{\n"
2454  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2455 "}\n"
2456 "offs = (etiss_int64)cast_0 + imm_extended;\n"
2457 #if RISCV64_DEBUG_CALL
2458 "printf(\"offs = %#lx\\n\",offs); \n"
2459 #endif
2460 "if(" + toString(rd) + " != 0)\n"
2461 "{\n"
2462  "etiss_uint16 MEM_offs;\n"
2463  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
2464  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,2);\n"
2465  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)MEM_offs;\n"
2466  #if RISCV64_DEBUG_CALL
2467  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2468  #endif
2469 "}\n"
2470 
2471 
2472  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2473 
2474  "return exception;\n"
2475 ;
2476 return true;
2477 },
2478 0,
2479 nullptr
2480 );
2481 //-------------------------------------------------------------------------------------------------------------------
2482 static InstructionDefinition csrrwi_rd_csr_zimm(
2483  ISA32_RISCV64,
2484  "csrrwi",
2485  (uint32_t)0x5073,
2486  (uint32_t) 0x707f,
2487  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2488  {
2489  etiss_uint64 rd = 0;
2490  static BitArrayRange R_rd_0 (11,7);
2491  etiss_uint64 rd_0 = R_rd_0.read(ba);
2492  rd += rd_0;
2493  etiss_uint64 csr = 0;
2494  static BitArrayRange R_csr_0 (31,20);
2495  etiss_uint64 csr_0 = R_csr_0.read(ba);
2496  csr += csr_0;
2497  etiss_uint64 zimm = 0;
2498  static BitArrayRange R_zimm_0 (19,15);
2499  etiss_uint64 zimm_0 = R_zimm_0.read(ba);
2500  zimm += zimm_0;
2501  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2502  partInit.getAffectedRegisters().add(reg_name[rd],64);
2503  partInit.getAffectedRegisters().add("instructionPointer",64);
2504  partInit.code() = std::string("//csrrwi\n")+
2505  "etiss_uint32 temp = 0;\n"
2506  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2507  #if RISCV64_Pipeline1
2508  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2509  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2510  "etiss_uint32 num_stages = 4;\n"
2511  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2512  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2513  #endif
2514  #if RISCV64_Pipeline2
2515  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2516  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2517  "etiss_uint32 num_stages = 4;\n"
2518  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2519  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2520  #endif
2521 
2522  "etiss_int64 mAddr = 0;\n"
2523  "etiss_int64 writeMask = 0;\n"
2524  "etiss_int64 writeMaskU = 0;\n"
2525  "etiss_int64 sAddr = 0;\n"
2526  "etiss_int64 writeMaskS = 0;\n"
2527  "etiss_int64 uAddr = 0;\n"
2528  "etiss_int64 writeMaskM = 0;\n"
2529 
2530 "if(" + toString(rd) + " != 0)\n"
2531 "{\n"
2532  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
2533  #if RISCV64_DEBUG_CALL
2534  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2535  #endif
2536 "}\n"
2537 
2538 "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
2539 "{\n"
2540  "uAddr = 0;\n"
2541  #if RISCV64_DEBUG_CALL
2542  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2543  #endif
2544  "sAddr = 256;\n"
2545  #if RISCV64_DEBUG_CALL
2546  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2547  #endif
2548  "mAddr = 768;\n"
2549  #if RISCV64_DEBUG_CALL
2550  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2551  #endif
2552  "writeMaskM = -9223372036846388805;\n"
2553  #if RISCV64_DEBUG_CALL
2554  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2555  #endif
2556  "writeMaskS = -9223372036853866189;\n"
2557  #if RISCV64_DEBUG_CALL
2558  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2559  #endif
2560  "writeMaskU = -9223372036853866479;\n"
2561  #if RISCV64_DEBUG_CALL
2562  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2563  #endif
2564 "}\n"
2565 
2566 "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
2567 "{\n"
2568  "uAddr = 68;\n"
2569  #if RISCV64_DEBUG_CALL
2570  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2571  #endif
2572  "sAddr = 324;\n"
2573  #if RISCV64_DEBUG_CALL
2574  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2575  #endif
2576  "mAddr = 836;\n"
2577  #if RISCV64_DEBUG_CALL
2578  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2579  #endif
2580  "writeMaskM = 3003;\n"
2581  #if RISCV64_DEBUG_CALL
2582  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2583  #endif
2584  "writeMaskS = 819;\n"
2585  #if RISCV64_DEBUG_CALL
2586  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2587  #endif
2588  "writeMaskU = 273;\n"
2589  #if RISCV64_DEBUG_CALL
2590  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2591  #endif
2592 "}\n"
2593 
2594 "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
2595 "{\n"
2596  "uAddr = 4;\n"
2597  #if RISCV64_DEBUG_CALL
2598  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2599  #endif
2600  "sAddr = 260;\n"
2601  #if RISCV64_DEBUG_CALL
2602  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2603  #endif
2604  "mAddr = 772;\n"
2605  #if RISCV64_DEBUG_CALL
2606  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2607  #endif
2608  "writeMaskM = 3003;\n"
2609  #if RISCV64_DEBUG_CALL
2610  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2611  #endif
2612  "writeMaskS = 819;\n"
2613  #if RISCV64_DEBUG_CALL
2614  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2615  #endif
2616  "writeMaskU = 273;\n"
2617  #if RISCV64_DEBUG_CALL
2618  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2619  #endif
2620 "}\n"
2621 
2622 "if(uAddr != sAddr)\n"
2623 "{\n"
2624  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
2625  "{\n"
2626  "writeMask = writeMaskM;\n"
2627  #if RISCV64_DEBUG_CALL
2628  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
2629  #endif
2630  "}\n"
2631 
2632  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
2633  "{\n"
2634  "writeMask = writeMaskS;\n"
2635  #if RISCV64_DEBUG_CALL
2636  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
2637  #endif
2638  "}\n"
2639 
2640  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
2641  "{\n"
2642  "writeMask = writeMaskU;\n"
2643  #if RISCV64_DEBUG_CALL
2644  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
2645  #endif
2646  "}\n"
2647 
2648  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((etiss_uint64)" + toString(zimm) + " & writeMask))&0xffffffffffffffff;\n"
2649  #if RISCV64_DEBUG_CALL
2650  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
2651  #endif
2652  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
2653  #if RISCV64_DEBUG_CALL
2654  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
2655  #endif
2656  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
2657  #if RISCV64_DEBUG_CALL
2658  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
2659  #endif
2660 "}\n"
2661 
2662 "else\n"
2663 "{\n"
2664  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (etiss_uint64)" + toString(zimm) + ";\n"
2665  #if RISCV64_DEBUG_CALL
2666  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
2667  #endif
2668 "}\n"
2669 
2670  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2671 
2672 ;
2673 return true;
2674 },
2675 0,
2676 nullptr
2677 );
2678 //-------------------------------------------------------------------------------------------------------------------
2679 static InstructionDefinition bltu_rs1_rs2_imm(
2680  ISA32_RISCV64,
2681  "bltu",
2682  (uint32_t)0x6063,
2683  (uint32_t) 0x707f,
2684  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2685  {
2686  etiss_uint64 rs2 = 0;
2687  static BitArrayRange R_rs2_0 (24,20);
2688  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
2689  rs2 += rs2_0;
2690  etiss_uint64 rs1 = 0;
2691  static BitArrayRange R_rs1_0 (19,15);
2692  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2693  rs1 += rs1_0;
2694  etiss_int64 imm = 0;
2695  static BitArrayRange R_imm_12 (31,31);
2696  etiss_int64 imm_12 = R_imm_12.read(ba);
2697  imm += imm_12<<12;
2698  static BitArrayRange R_imm_5 (30,25);
2699  etiss_int64 imm_5 = R_imm_5.read(ba);
2700  imm += imm_5<<5;
2701  static BitArrayRange R_imm_1 (11,8);
2702  etiss_int64 imm_1 = R_imm_1.read(ba);
2703  imm += imm_1<<1;
2704  static BitArrayRange R_imm_11 (7,7);
2705  etiss_int64 imm_11 = R_imm_11.read(ba);
2706  imm += imm_11<<11;
2707  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2708  partInit.getRegisterDependencies().add(reg_name[rs2],64);
2709  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2710  partInit.getAffectedRegisters().add("instructionPointer",64);
2711  partInit.code() = std::string("//bltu\n")+
2712  "etiss_uint32 temp = 0;\n"
2713  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2714  #if RISCV64_Pipeline1
2715  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2716  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2717  "etiss_uint32 num_stages = 4;\n"
2718  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2719  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2720  #endif
2721  #if RISCV64_Pipeline2
2722  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2723  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2724  "etiss_uint32 num_stages = 4;\n"
2725  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2726  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2727  #endif
2728 
2729  "etiss_int64 imm_extended = 0;\n"
2730  "etiss_int64 choose1 = 0;\n"
2731 
2732 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
2733 "{\n"
2734  "imm_extended = 0;\n"
2735  #if RISCV64_DEBUG_CALL
2736  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2737  #endif
2738 "}\n"
2739 
2740 "else\n"
2741 "{\n"
2742  "imm_extended = 4294967295;\n"
2743  #if RISCV64_DEBUG_CALL
2744  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2745  #endif
2746  "imm_extended = (imm_extended << 32);\n"
2747  #if RISCV64_DEBUG_CALL
2748  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2749  #endif
2750  "imm_extended = imm_extended + 4294959104;\n"
2751  #if RISCV64_DEBUG_CALL
2752  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2753  #endif
2754 "}\n"
2755 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2756 #if RISCV64_DEBUG_CALL
2757 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2758 #endif
2759 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + "] < *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
2760 "{\n"
2761  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
2762  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2763  "{\n"
2764  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2765  "}\n"
2766  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
2767  #if RISCV64_DEBUG_CALL
2768  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2769  #endif
2770 // Explicit assignment to PC
2771 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2772 "}\n"
2773 
2774 "else\n"
2775 "{\n"
2776  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
2777  #if RISCV64_DEBUG_CALL
2778  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2779  #endif
2780 "}\n"
2781 "cpu->instructionPointer = choose1;\n"
2782 #if RISCV64_DEBUG_CALL
2783 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
2784 #endif
2785 
2786  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
2787 
2788  "return 0;\n"
2789 ;
2790 return true;
2791 },
2792 0,
2793 nullptr
2794 );
2795 //-------------------------------------------------------------------------------------------------------------------
2796 static InstructionDefinition ori_rd_rs1_imm(
2797  ISA32_RISCV64,
2798  "ori",
2799  (uint32_t)0x6013,
2800  (uint32_t) 0x707f,
2801  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2802  {
2803  etiss_uint64 rs1 = 0;
2804  static BitArrayRange R_rs1_0 (19,15);
2805  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2806  rs1 += rs1_0;
2807  etiss_uint64 rd = 0;
2808  static BitArrayRange R_rd_0 (11,7);
2809  etiss_uint64 rd_0 = R_rd_0.read(ba);
2810  rd += rd_0;
2811  etiss_int64 imm = 0;
2812  static BitArrayRange R_imm_0 (31,20);
2813  etiss_int64 imm_0 = R_imm_0.read(ba);
2814  imm += imm_0;
2815  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2816  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2817  partInit.getAffectedRegisters().add(reg_name[rd],64);
2818  partInit.getAffectedRegisters().add("instructionPointer",64);
2819  partInit.code() = std::string("//ori\n")+
2820  "etiss_uint32 temp = 0;\n"
2821  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2822  #if RISCV64_Pipeline1
2823  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2824  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2825  "etiss_uint32 num_stages = 4;\n"
2826  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2827  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2828  #endif
2829  #if RISCV64_Pipeline2
2830  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2831  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2832  "etiss_uint32 num_stages = 4;\n"
2833  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2834  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2835  #endif
2836 
2837  "etiss_int64 imm_extended = 0;\n"
2838 
2839 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
2840 "{\n"
2841  "imm_extended = 0;\n"
2842  #if RISCV64_DEBUG_CALL
2843  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2844  #endif
2845 "}\n"
2846 
2847 "else\n"
2848 "{\n"
2849  "imm_extended = 4294967295;\n"
2850  #if RISCV64_DEBUG_CALL
2851  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2852  #endif
2853  "imm_extended = (imm_extended << 32);\n"
2854  #if RISCV64_DEBUG_CALL
2855  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2856  #endif
2857  "imm_extended = imm_extended + 4294963200;\n"
2858  #if RISCV64_DEBUG_CALL
2859  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2860  #endif
2861 "}\n"
2862 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2863 #if RISCV64_DEBUG_CALL
2864 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2865 #endif
2866 "if(" + toString(rd) + " != 0)\n"
2867 "{\n"
2868  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2869  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2870  "{\n"
2871  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2872  "}\n"
2873  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 | imm_extended);\n"
2874  #if RISCV64_DEBUG_CALL
2875  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2876  #endif
2877 "}\n"
2878 
2879 
2880  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2881 
2882 ;
2883 return true;
2884 },
2885 0,
2886 nullptr
2887 );
2888 //-------------------------------------------------------------------------------------------------------------------
2889 static InstructionDefinition csrrsi_rd_csr_zimm(
2890  ISA32_RISCV64,
2891  "csrrsi",
2892  (uint32_t)0x6073,
2893  (uint32_t) 0x707f,
2894  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2895  {
2896  etiss_uint64 rd = 0;
2897  static BitArrayRange R_rd_0 (11,7);
2898  etiss_uint64 rd_0 = R_rd_0.read(ba);
2899  rd += rd_0;
2900  etiss_uint64 csr = 0;
2901  static BitArrayRange R_csr_0 (31,20);
2902  etiss_uint64 csr_0 = R_csr_0.read(ba);
2903  csr += csr_0;
2904  etiss_uint64 zimm = 0;
2905  static BitArrayRange R_zimm_0 (19,15);
2906  etiss_uint64 zimm_0 = R_zimm_0.read(ba);
2907  zimm += zimm_0;
2908  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2909  partInit.getAffectedRegisters().add(reg_name[rd],64);
2910  partInit.getAffectedRegisters().add("instructionPointer",64);
2911  partInit.code() = std::string("//csrrsi\n")+
2912  "etiss_uint32 temp = 0;\n"
2913  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2914  #if RISCV64_Pipeline1
2915  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2916  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2917  "etiss_uint32 num_stages = 4;\n"
2918  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2919  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2920  #endif
2921  #if RISCV64_Pipeline2
2922  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2923  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2924  "etiss_uint32 num_stages = 4;\n"
2925  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2926  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2927  #endif
2928 
2929  "etiss_uint64 res = 0;\n"
2930  "etiss_int64 mAddr = 0;\n"
2931  "etiss_int64 writeMask = 0;\n"
2932  "etiss_int64 writeMaskU = 0;\n"
2933  "etiss_int64 sAddr = 0;\n"
2934  "etiss_int64 writeMaskS = 0;\n"
2935  "etiss_int64 uAddr = 0;\n"
2936  "etiss_int64 writeMaskM = 0;\n"
2937 
2938 "res = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
2939 #if RISCV64_DEBUG_CALL
2940 "printf(\"res = %#lx\\n\",res); \n"
2941 #endif
2942 "if(" + toString(zimm) + " != 0)\n"
2943 "{\n"
2944  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
2945  "{\n"
2946  "uAddr = 0;\n"
2947  #if RISCV64_DEBUG_CALL
2948  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2949  #endif
2950  "sAddr = 256;\n"
2951  #if RISCV64_DEBUG_CALL
2952  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2953  #endif
2954  "mAddr = 768;\n"
2955  #if RISCV64_DEBUG_CALL
2956  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2957  #endif
2958  "writeMaskM = -9223372036846388805;\n"
2959  #if RISCV64_DEBUG_CALL
2960  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2961  #endif
2962  "writeMaskS = -9223372036853866189;\n"
2963  #if RISCV64_DEBUG_CALL
2964  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2965  #endif
2966  "writeMaskU = -9223372036853866479;\n"
2967  #if RISCV64_DEBUG_CALL
2968  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2969  #endif
2970  "}\n"
2971 
2972  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
2973  "{\n"
2974  "uAddr = 68;\n"
2975  #if RISCV64_DEBUG_CALL
2976  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2977  #endif
2978  "sAddr = 324;\n"
2979  #if RISCV64_DEBUG_CALL
2980  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2981  #endif
2982  "mAddr = 836;\n"
2983  #if RISCV64_DEBUG_CALL
2984  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2985  #endif
2986  "writeMaskM = 3003;\n"
2987  #if RISCV64_DEBUG_CALL
2988  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2989  #endif
2990  "writeMaskS = 819;\n"
2991  #if RISCV64_DEBUG_CALL
2992  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2993  #endif
2994  "writeMaskU = 273;\n"
2995  #if RISCV64_DEBUG_CALL
2996  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2997  #endif
2998  "}\n"
2999 
3000  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
3001  "{\n"
3002  "uAddr = 4;\n"
3003  #if RISCV64_DEBUG_CALL
3004  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
3005  #endif
3006  "sAddr = 260;\n"
3007  #if RISCV64_DEBUG_CALL
3008  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
3009  #endif
3010  "mAddr = 772;\n"
3011  #if RISCV64_DEBUG_CALL
3012  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
3013  #endif
3014  "writeMaskM = 3003;\n"
3015  #if RISCV64_DEBUG_CALL
3016  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
3017  #endif
3018  "writeMaskS = 819;\n"
3019  #if RISCV64_DEBUG_CALL
3020  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
3021  #endif
3022  "writeMaskU = 273;\n"
3023  #if RISCV64_DEBUG_CALL
3024  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
3025  #endif
3026  "}\n"
3027 
3028  "if(uAddr != sAddr)\n"
3029  "{\n"
3030  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
3031  "{\n"
3032  "writeMask = writeMaskM;\n"
3033  #if RISCV64_DEBUG_CALL
3034  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3035  #endif
3036  "}\n"
3037 
3038  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
3039  "{\n"
3040  "writeMask = writeMaskS;\n"
3041  #if RISCV64_DEBUG_CALL
3042  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3043  #endif
3044  "}\n"
3045 
3046  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
3047  "{\n"
3048  "writeMask = writeMaskU;\n"
3049  #if RISCV64_DEBUG_CALL
3050  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3051  #endif
3052  "}\n"
3053 
3054  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((res | (etiss_uint64)" + toString(zimm) + ") & writeMask))&0xffffffffffffffff;\n"
3055  #if RISCV64_DEBUG_CALL
3056  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
3057  #endif
3058  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
3059  #if RISCV64_DEBUG_CALL
3060  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
3061  #endif
3062  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
3063  #if RISCV64_DEBUG_CALL
3064  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
3065  #endif
3066  "}\n"
3067 
3068  "else\n"
3069  "{\n"
3070  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (res | (etiss_uint64)" + toString(zimm) + ");\n"
3071  #if RISCV64_DEBUG_CALL
3072  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
3073  #endif
3074  "}\n"
3075 "}\n"
3076 
3077 "if(" + toString(rd) + " != 0)\n"
3078 "{\n"
3079  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
3080  #if RISCV64_DEBUG_CALL
3081  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3082  #endif
3083 "}\n"
3084 
3085 
3086  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3087 
3088 ;
3089 return true;
3090 },
3091 0,
3092 nullptr
3093 );
3094 //-------------------------------------------------------------------------------------------------------------------
3095 static InstructionDefinition lwu_rd_imm_rs1_(
3096  ISA32_RISCV64,
3097  "lwu",
3098  (uint32_t)0x6003,
3099  (uint32_t) 0x707f,
3100  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3101  {
3102  etiss_uint64 rs1 = 0;
3103  static BitArrayRange R_rs1_0 (19,15);
3104  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3105  rs1 += rs1_0;
3106  etiss_uint64 rd = 0;
3107  static BitArrayRange R_rd_0 (11,7);
3108  etiss_uint64 rd_0 = R_rd_0.read(ba);
3109  rd += rd_0;
3110  etiss_int64 imm = 0;
3111  static BitArrayRange R_imm_0 (31,20);
3112  etiss_int64 imm_0 = R_imm_0.read(ba);
3113  imm += imm_0;
3114  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3115  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3116  partInit.getAffectedRegisters().add(reg_name[rd],64);
3117  partInit.getAffectedRegisters().add("instructionPointer",64);
3118  partInit.code() = std::string("//lwu\n")+
3119  "etiss_uint32 exception = 0;\n"
3120  "etiss_uint32 temp = 0;\n"
3121  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3122  #if RISCV64_Pipeline1
3123  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3124  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3125  "etiss_uint32 num_stages = 4;\n"
3126  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3127  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3128  #endif
3129  #if RISCV64_Pipeline2
3130  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3131  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3132  "etiss_uint32 num_stages = 4;\n"
3133  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3134  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3135  #endif
3136 
3137  "etiss_int64 offs = 0;\n"
3138  "etiss_int64 imm_extended = 0;\n"
3139 
3140 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3141 "{\n"
3142  "imm_extended = 0;\n"
3143  #if RISCV64_DEBUG_CALL
3144  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3145  #endif
3146 "}\n"
3147 
3148 "else\n"
3149 "{\n"
3150  "imm_extended = 4294967295;\n"
3151  #if RISCV64_DEBUG_CALL
3152  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3153  #endif
3154  "imm_extended = (imm_extended << 32);\n"
3155  #if RISCV64_DEBUG_CALL
3156  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3157  #endif
3158  "imm_extended = imm_extended + 4294963200;\n"
3159  #if RISCV64_DEBUG_CALL
3160  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3161  #endif
3162 "}\n"
3163 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3164 #if RISCV64_DEBUG_CALL
3165 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3166 #endif
3167 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3168 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3169 "{\n"
3170  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3171 "}\n"
3172 "offs = (etiss_int64)cast_0 + imm_extended;\n"
3173 #if RISCV64_DEBUG_CALL
3174 "printf(\"offs = %#lx\\n\",offs); \n"
3175 #endif
3176 "if(" + toString(rd) + " != 0)\n"
3177 "{\n"
3178  "etiss_uint32 MEM_offs;\n"
3179  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
3180  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
3181  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)MEM_offs;\n"
3182  #if RISCV64_DEBUG_CALL
3183  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3184  #endif
3185 "}\n"
3186 
3187 
3188  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3189 
3190  "return exception;\n"
3191 ;
3192 return true;
3193 },
3194 0,
3195 nullptr
3196 );
3197 //-------------------------------------------------------------------------------------------------------------------
3198 static InstructionDefinition bgeu_rs1_rs2_imm(
3199  ISA32_RISCV64,
3200  "bgeu",
3201  (uint32_t)0x7063,
3202  (uint32_t) 0x707f,
3203  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3204  {
3205  etiss_uint64 rs2 = 0;
3206  static BitArrayRange R_rs2_0 (24,20);
3207  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
3208  rs2 += rs2_0;
3209  etiss_uint64 rs1 = 0;
3210  static BitArrayRange R_rs1_0 (19,15);
3211  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3212  rs1 += rs1_0;
3213  etiss_int64 imm = 0;
3214  static BitArrayRange R_imm_12 (31,31);
3215  etiss_int64 imm_12 = R_imm_12.read(ba);
3216  imm += imm_12<<12;
3217  static BitArrayRange R_imm_5 (30,25);
3218  etiss_int64 imm_5 = R_imm_5.read(ba);
3219  imm += imm_5<<5;
3220  static BitArrayRange R_imm_1 (11,8);
3221  etiss_int64 imm_1 = R_imm_1.read(ba);
3222  imm += imm_1<<1;
3223  static BitArrayRange R_imm_11 (7,7);
3224  etiss_int64 imm_11 = R_imm_11.read(ba);
3225  imm += imm_11<<11;
3226  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3227  partInit.getRegisterDependencies().add(reg_name[rs2],64);
3228  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3229  partInit.getAffectedRegisters().add("instructionPointer",64);
3230  partInit.code() = std::string("//bgeu\n")+
3231  "etiss_uint32 temp = 0;\n"
3232  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3233  #if RISCV64_Pipeline1
3234  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3235  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3236  "etiss_uint32 num_stages = 4;\n"
3237  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3238  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3239  #endif
3240  #if RISCV64_Pipeline2
3241  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3242  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3243  "etiss_uint32 num_stages = 4;\n"
3244  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3245  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3246  #endif
3247 
3248  "etiss_int64 imm_extended = 0;\n"
3249  "etiss_int64 choose1 = 0;\n"
3250 
3251 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
3252 "{\n"
3253  "imm_extended = 0;\n"
3254  #if RISCV64_DEBUG_CALL
3255  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3256  #endif
3257 "}\n"
3258 
3259 "else\n"
3260 "{\n"
3261  "imm_extended = 4294967295;\n"
3262  #if RISCV64_DEBUG_CALL
3263  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3264  #endif
3265  "imm_extended = (imm_extended << 32);\n"
3266  #if RISCV64_DEBUG_CALL
3267  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3268  #endif
3269  "imm_extended = imm_extended + 4294959104;\n"
3270  #if RISCV64_DEBUG_CALL
3271  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3272  #endif
3273 "}\n"
3274 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3275 #if RISCV64_DEBUG_CALL
3276 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3277 #endif
3278 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + "] >= *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
3279 "{\n"
3280  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
3281  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3282  "{\n"
3283  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3284  "}\n"
3285  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
3286  #if RISCV64_DEBUG_CALL
3287  "printf(\"choose1 = %#lx\\n\",choose1); \n"
3288  #endif
3289 // Explicit assignment to PC
3290 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3291 "}\n"
3292 
3293 "else\n"
3294 "{\n"
3295  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
3296  #if RISCV64_DEBUG_CALL
3297  "printf(\"choose1 = %#lx\\n\",choose1); \n"
3298  #endif
3299 "}\n"
3300 "cpu->instructionPointer = choose1;\n"
3301 #if RISCV64_DEBUG_CALL
3302 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
3303 #endif
3304 
3305  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
3306 
3307  "return 0;\n"
3308 ;
3309 return true;
3310 },
3311 0,
3312 nullptr
3313 );
3314 //-------------------------------------------------------------------------------------------------------------------
3315 static InstructionDefinition andi_rd_rs1_imm(
3316  ISA32_RISCV64,
3317  "andi",
3318  (uint32_t)0x7013,
3319  (uint32_t) 0x707f,
3320  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3321  {
3322  etiss_uint64 rs1 = 0;
3323  static BitArrayRange R_rs1_0 (19,15);
3324  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3325  rs1 += rs1_0;
3326  etiss_uint64 rd = 0;
3327  static BitArrayRange R_rd_0 (11,7);
3328  etiss_uint64 rd_0 = R_rd_0.read(ba);
3329  rd += rd_0;
3330  etiss_int64 imm = 0;
3331  static BitArrayRange R_imm_0 (31,20);
3332  etiss_int64 imm_0 = R_imm_0.read(ba);
3333  imm += imm_0;
3334  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3335  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3336  partInit.getAffectedRegisters().add(reg_name[rd],64);
3337  partInit.getAffectedRegisters().add("instructionPointer",64);
3338  partInit.code() = std::string("//andi\n")+
3339  "etiss_uint32 temp = 0;\n"
3340  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3341  #if RISCV64_Pipeline1
3342  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3343  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3344  "etiss_uint32 num_stages = 4;\n"
3345  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3346  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3347  #endif
3348  #if RISCV64_Pipeline2
3349  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3350  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3351  "etiss_uint32 num_stages = 4;\n"
3352  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3353  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3354  #endif
3355 
3356  "etiss_int64 imm_extended = 0;\n"
3357 
3358 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3359 "{\n"
3360  "imm_extended = 0;\n"
3361  #if RISCV64_DEBUG_CALL
3362  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3363  #endif
3364 "}\n"
3365 
3366 "else\n"
3367 "{\n"
3368  "imm_extended = 4294967295;\n"
3369  #if RISCV64_DEBUG_CALL
3370  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3371  #endif
3372  "imm_extended = (imm_extended << 32);\n"
3373  #if RISCV64_DEBUG_CALL
3374  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3375  #endif
3376  "imm_extended = imm_extended + 4294963200;\n"
3377  #if RISCV64_DEBUG_CALL
3378  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3379  #endif
3380 "}\n"
3381 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3382 #if RISCV64_DEBUG_CALL
3383 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3384 #endif
3385 "if(" + toString(rd) + " != 0)\n"
3386 "{\n"
3387  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3388  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3389  "{\n"
3390  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3391  "}\n"
3392  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 & imm_extended);\n"
3393  #if RISCV64_DEBUG_CALL
3394  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3395  #endif
3396 "}\n"
3397 
3398 
3399  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3400 
3401 ;
3402 return true;
3403 },
3404 0,
3405 nullptr
3406 );
3407 //-------------------------------------------------------------------------------------------------------------------
3408 static InstructionDefinition csrrci_rd_csr_zimm(
3409  ISA32_RISCV64,
3410  "csrrci",
3411  (uint32_t)0x7073,
3412  (uint32_t) 0x707f,
3413  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3414  {
3415  etiss_uint64 rd = 0;
3416  static BitArrayRange R_rd_0 (11,7);
3417  etiss_uint64 rd_0 = R_rd_0.read(ba);
3418  rd += rd_0;
3419  etiss_uint64 csr = 0;
3420  static BitArrayRange R_csr_0 (31,20);
3421  etiss_uint64 csr_0 = R_csr_0.read(ba);
3422  csr += csr_0;
3423  etiss_uint64 zimm = 0;
3424  static BitArrayRange R_zimm_0 (19,15);
3425  etiss_uint64 zimm_0 = R_zimm_0.read(ba);
3426  zimm += zimm_0;
3427  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3428  partInit.getAffectedRegisters().add(reg_name[rd],64);
3429  partInit.getAffectedRegisters().add("instructionPointer",64);
3430  partInit.code() = std::string("//csrrci\n")+
3431  "etiss_uint32 temp = 0;\n"
3432  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3433  #if RISCV64_Pipeline1
3434  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3435  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3436  "etiss_uint32 num_stages = 4;\n"
3437  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3438  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3439  #endif
3440  #if RISCV64_Pipeline2
3441  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3442  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3443  "etiss_uint32 num_stages = 4;\n"
3444  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3445  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3446  #endif
3447 
3448  "etiss_uint64 res = 0;\n"
3449  "etiss_int64 mAddr = 0;\n"
3450  "etiss_int64 writeMask = 0;\n"
3451  "etiss_int64 writeMaskU = 0;\n"
3452  "etiss_int64 sAddr = 0;\n"
3453  "etiss_int64 writeMaskS = 0;\n"
3454  "etiss_int64 uAddr = 0;\n"
3455  "etiss_int64 writeMaskM = 0;\n"
3456 
3457 "res = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
3458 #if RISCV64_DEBUG_CALL
3459 "printf(\"res = %#lx\\n\",res); \n"
3460 #endif
3461 "if(" + toString(rd) + " != 0)\n"
3462 "{\n"
3463  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
3464  #if RISCV64_DEBUG_CALL
3465  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3466  #endif
3467 "}\n"
3468 
3469 "if(" + toString(zimm) + " != 0)\n"
3470 "{\n"
3471  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
3472  "{\n"
3473  "uAddr = 0;\n"
3474  #if RISCV64_DEBUG_CALL
3475  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
3476  #endif
3477  "sAddr = 256;\n"
3478  #if RISCV64_DEBUG_CALL
3479  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
3480  #endif
3481  "mAddr = 768;\n"
3482  #if RISCV64_DEBUG_CALL
3483  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
3484  #endif
3485  "writeMaskM = -9223372036846388805;\n"
3486  #if RISCV64_DEBUG_CALL
3487  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
3488  #endif
3489  "writeMaskS = -9223372036853866189;\n"
3490  #if RISCV64_DEBUG_CALL
3491  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
3492  #endif
3493  "writeMaskU = -9223372036853866479;\n"
3494  #if RISCV64_DEBUG_CALL
3495  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
3496  #endif
3497  "}\n"
3498 
3499  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
3500  "{\n"
3501  "uAddr = 68;\n"
3502  #if RISCV64_DEBUG_CALL
3503  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
3504  #endif
3505  "sAddr = 324;\n"
3506  #if RISCV64_DEBUG_CALL
3507  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
3508  #endif
3509  "mAddr = 836;\n"
3510  #if RISCV64_DEBUG_CALL
3511  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
3512  #endif
3513  "writeMaskM = 3003;\n"
3514  #if RISCV64_DEBUG_CALL
3515  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
3516  #endif
3517  "writeMaskS = 819;\n"
3518  #if RISCV64_DEBUG_CALL
3519  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
3520  #endif
3521  "writeMaskU = 273;\n"
3522  #if RISCV64_DEBUG_CALL
3523  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
3524  #endif
3525  "}\n"
3526 
3527  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
3528  "{\n"
3529  "uAddr = 4;\n"
3530  #if RISCV64_DEBUG_CALL
3531  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
3532  #endif
3533  "sAddr = 260;\n"
3534  #if RISCV64_DEBUG_CALL
3535  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
3536  #endif
3537  "mAddr = 772;\n"
3538  #if RISCV64_DEBUG_CALL
3539  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
3540  #endif
3541  "writeMaskM = 3003;\n"
3542  #if RISCV64_DEBUG_CALL
3543  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
3544  #endif
3545  "writeMaskS = 819;\n"
3546  #if RISCV64_DEBUG_CALL
3547  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
3548  #endif
3549  "writeMaskU = 273;\n"
3550  #if RISCV64_DEBUG_CALL
3551  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
3552  #endif
3553  "}\n"
3554 
3555  "if(uAddr != sAddr)\n"
3556  "{\n"
3557  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
3558  "{\n"
3559  "writeMask = writeMaskM;\n"
3560  #if RISCV64_DEBUG_CALL
3561  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3562  #endif
3563  "}\n"
3564 
3565  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
3566  "{\n"
3567  "writeMask = writeMaskS;\n"
3568  #if RISCV64_DEBUG_CALL
3569  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3570  #endif
3571  "}\n"
3572 
3573  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
3574  "{\n"
3575  "writeMask = writeMaskU;\n"
3576  #if RISCV64_DEBUG_CALL
3577  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3578  #endif
3579  "}\n"
3580 
3581  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((res & ~(etiss_uint64)" + toString(zimm) + ") & writeMask))&0xffffffffffffffff&0xffffffffffffffff;\n"
3582  #if RISCV64_DEBUG_CALL
3583  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
3584  #endif
3585  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
3586  #if RISCV64_DEBUG_CALL
3587  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
3588  #endif
3589  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
3590  #if RISCV64_DEBUG_CALL
3591  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
3592  #endif
3593  "}\n"
3594 
3595  "else\n"
3596  "{\n"
3597  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (res & ~(etiss_uint64)" + toString(zimm) + ")&0xffffffffffffffff;\n"
3598  #if RISCV64_DEBUG_CALL
3599  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
3600  #endif
3601  "}\n"
3602 "}\n"
3603 
3604 
3605  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3606 
3607 ;
3608 return true;
3609 },
3610 0,
3611 nullptr
3612 );
3613 //-------------------------------------------------------------------------------------------------------------------
3614 static InstructionDefinition lw_rd_imm_rs1_(
3615  ISA32_RISCV64,
3616  "lw",
3617  (uint32_t)0x2003,
3618  (uint32_t) 0x707f,
3619  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3620  {
3621  etiss_uint64 rs1 = 0;
3622  static BitArrayRange R_rs1_0 (19,15);
3623  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3624  rs1 += rs1_0;
3625  etiss_uint64 rd = 0;
3626  static BitArrayRange R_rd_0 (11,7);
3627  etiss_uint64 rd_0 = R_rd_0.read(ba);
3628  rd += rd_0;
3629  etiss_int64 imm = 0;
3630  static BitArrayRange R_imm_0 (31,20);
3631  etiss_int64 imm_0 = R_imm_0.read(ba);
3632  imm += imm_0;
3633  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3634  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3635  partInit.getAffectedRegisters().add(reg_name[rd],64);
3636  partInit.getAffectedRegisters().add("instructionPointer",64);
3637  partInit.code() = std::string("//lw\n")+
3638  "etiss_uint32 exception = 0;\n"
3639  "etiss_uint32 temp = 0;\n"
3640  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3641  #if RISCV64_Pipeline1
3642  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3643  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3644  "etiss_uint32 num_stages = 4;\n"
3645  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3646  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3647  #endif
3648  #if RISCV64_Pipeline2
3649  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3650  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3651  "etiss_uint32 num_stages = 4;\n"
3652  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3653  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3654  #endif
3655 
3656  "etiss_int64 offs = 0;\n"
3657  "etiss_int64 imm_extended = 0;\n"
3658 
3659 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3660 "{\n"
3661  "imm_extended = 0;\n"
3662  #if RISCV64_DEBUG_CALL
3663  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3664  #endif
3665 "}\n"
3666 
3667 "else\n"
3668 "{\n"
3669  "imm_extended = 4294967295;\n"
3670  #if RISCV64_DEBUG_CALL
3671  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3672  #endif
3673  "imm_extended = (imm_extended << 32);\n"
3674  #if RISCV64_DEBUG_CALL
3675  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3676  #endif
3677  "imm_extended = imm_extended + 4294963200;\n"
3678  #if RISCV64_DEBUG_CALL
3679  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3680  #endif
3681 "}\n"
3682 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3683 #if RISCV64_DEBUG_CALL
3684 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3685 #endif
3686 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3687 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3688 "{\n"
3689  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3690 "}\n"
3691 "offs = (etiss_int64)cast_0 + imm_extended;\n"
3692 #if RISCV64_DEBUG_CALL
3693 "printf(\"offs = %#lx\\n\",offs); \n"
3694 #endif
3695 "if(" + toString(rd) + " != 0)\n"
3696 "{\n"
3697  "etiss_uint32 MEM_offs;\n"
3698  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
3699  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
3700  "etiss_int32 cast_1 = MEM_offs; \n"
3701  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
3702  "{\n"
3703  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
3704  "}\n"
3705  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
3706  #if RISCV64_DEBUG_CALL
3707  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3708  #endif
3709 "}\n"
3710 
3711 
3712  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3713 
3714  "return exception;\n"
3715 ;
3716 return true;
3717 },
3718 0,
3719 nullptr
3720 );
3721 //-------------------------------------------------------------------------------------------------------------------
3722 static InstructionDefinition sw_rs2_imm_rs1_(
3723  ISA32_RISCV64,
3724  "sw",
3725  (uint32_t)0x2023,
3726  (uint32_t) 0x707f,
3727  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3728  {
3729  etiss_uint64 rs2 = 0;
3730  static BitArrayRange R_rs2_0 (24,20);
3731  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
3732  rs2 += rs2_0;
3733  etiss_uint64 rs1 = 0;
3734  static BitArrayRange R_rs1_0 (19,15);
3735  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3736  rs1 += rs1_0;
3737  etiss_int64 imm = 0;
3738  static BitArrayRange R_imm_5 (31,25);
3739  etiss_int64 imm_5 = R_imm_5.read(ba);
3740  imm += imm_5<<5;
3741  static BitArrayRange R_imm_0 (11,7);
3742  etiss_int64 imm_0 = R_imm_0.read(ba);
3743  imm += imm_0;
3744  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3745  partInit.getRegisterDependencies().add(reg_name[rs2],64);
3746  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3747  partInit.getAffectedRegisters().add("instructionPointer",64);
3748  partInit.code() = std::string("//sw\n")+
3749  "etiss_uint32 exception = 0;\n"
3750  "etiss_uint32 temp = 0;\n"
3751  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3752  #if RISCV64_Pipeline1
3753  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3754  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3755  "etiss_uint32 num_stages = 4;\n"
3756  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3757  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3758  #endif
3759  #if RISCV64_Pipeline2
3760  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3761  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3762  "etiss_uint32 num_stages = 4;\n"
3763  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3764  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3765  #endif
3766 
3767  "etiss_int64 offs = 0;\n"
3768  "etiss_int64 imm_extended = 0;\n"
3769 
3770 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3771 "{\n"
3772  "imm_extended = 0;\n"
3773  #if RISCV64_DEBUG_CALL
3774  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3775  #endif
3776 "}\n"
3777 
3778 "else\n"
3779 "{\n"
3780  "imm_extended = 4294967295;\n"
3781  #if RISCV64_DEBUG_CALL
3782  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3783  #endif
3784  "imm_extended = (imm_extended << 32);\n"
3785  #if RISCV64_DEBUG_CALL
3786  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3787  #endif
3788  "imm_extended = imm_extended + 4294963200;\n"
3789  #if RISCV64_DEBUG_CALL
3790  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3791  #endif
3792 "}\n"
3793 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3794 #if RISCV64_DEBUG_CALL
3795 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3796 #endif
3797 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3798 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3799 "{\n"
3800  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3801 "}\n"
3802 "offs = (etiss_int64)cast_0 + imm_extended;\n"
3803 #if RISCV64_DEBUG_CALL
3804 "printf(\"offs = %#lx\\n\",offs); \n"
3805 #endif
3806  "etiss_uint32 MEM_offs;\n"
3807 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
3808 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
3809 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
3810 #if RISCV64_DEBUG_CALL
3811 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
3812 #endif
3813 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
3814 "{\n"
3815  "((RISCV64*)cpu)->RES = 0;\n"
3816  #if RISCV64_DEBUG_CALL
3817  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
3818  #endif
3819 "}\n"
3820 
3821 
3822  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3823 
3824  "return exception;\n"
3825 ;
3826 return true;
3827 },
3828 0,
3829 nullptr
3830 );
3831 //-------------------------------------------------------------------------------------------------------------------
3832 static InstructionDefinition slti_rd_rs1_imm(
3833  ISA32_RISCV64,
3834  "slti",
3835  (uint32_t)0x2013,
3836  (uint32_t) 0x707f,
3837  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3838  {
3839  etiss_uint64 rs1 = 0;
3840  static BitArrayRange R_rs1_0 (19,15);
3841  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3842  rs1 += rs1_0;
3843  etiss_uint64 rd = 0;
3844  static BitArrayRange R_rd_0 (11,7);
3845  etiss_uint64 rd_0 = R_rd_0.read(ba);
3846  rd += rd_0;
3847  etiss_int64 imm = 0;
3848  static BitArrayRange R_imm_0 (31,20);
3849  etiss_int64 imm_0 = R_imm_0.read(ba);
3850  imm += imm_0;
3851  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3852  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3853  partInit.getAffectedRegisters().add(reg_name[rd],64);
3854  partInit.getAffectedRegisters().add("instructionPointer",64);
3855  partInit.code() = std::string("//slti\n")+
3856  "etiss_uint32 temp = 0;\n"
3857  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3858  #if RISCV64_Pipeline1
3859  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3860  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3861  "etiss_uint32 num_stages = 4;\n"
3862  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3863  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3864  #endif
3865  #if RISCV64_Pipeline2
3866  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3867  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3868  "etiss_uint32 num_stages = 4;\n"
3869  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3870  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3871  #endif
3872 
3873  "etiss_int64 imm_extended = 0;\n"
3874  "etiss_int8 choose1 = 0;\n"
3875 
3876 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3877 "{\n"
3878  "imm_extended = 0;\n"
3879  #if RISCV64_DEBUG_CALL
3880  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3881  #endif
3882 "}\n"
3883 
3884 "else\n"
3885 "{\n"
3886  "imm_extended = 4294967295;\n"
3887  #if RISCV64_DEBUG_CALL
3888  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3889  #endif
3890  "imm_extended = (imm_extended << 32);\n"
3891  #if RISCV64_DEBUG_CALL
3892  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3893  #endif
3894  "imm_extended = imm_extended + 4294963200;\n"
3895  #if RISCV64_DEBUG_CALL
3896  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3897  #endif
3898 "}\n"
3899 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3900 #if RISCV64_DEBUG_CALL
3901 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3902 #endif
3903 "if(" + toString(rd) + " != 0)\n"
3904 "{\n"
3905  "etiss_int64 cast_0 = imm_extended; \n"
3906  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3907  "{\n"
3908  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3909  "}\n"
3910  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3911  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
3912  "{\n"
3913  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
3914  "}\n"
3915  "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n"
3916  "{\n"
3917  "choose1 = 1;\n"
3918  #if RISCV64_DEBUG_CALL
3919  "printf(\"choose1 = %#x\\n\",choose1); \n"
3920  #endif
3921  "}\n"
3922 
3923  "else\n"
3924  "{\n"
3925  "choose1 = 0;\n"
3926  #if RISCV64_DEBUG_CALL
3927  "printf(\"choose1 = %#x\\n\",choose1); \n"
3928  #endif
3929  "}\n"
3930  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = choose1;\n"
3931  #if RISCV64_DEBUG_CALL
3932  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3933  #endif
3934 "}\n"
3935 
3936 
3937  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3938 
3939 ;
3940 return true;
3941 },
3942 0,
3943 nullptr
3944 );
3945 //-------------------------------------------------------------------------------------------------------------------
3946 static InstructionDefinition csrrs_rd_csr_rs1(
3947  ISA32_RISCV64,
3948  "csrrs",
3949  (uint32_t)0x2073,
3950  (uint32_t) 0x707f,
3951  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3952  {
3953  etiss_uint64 rs1 = 0;
3954  static BitArrayRange R_rs1_0 (19,15);
3955  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3956  rs1 += rs1_0;
3957  etiss_uint64 rd = 0;
3958  static BitArrayRange R_rd_0 (11,7);
3959  etiss_uint64 rd_0 = R_rd_0.read(ba);
3960  rd += rd_0;
3961  etiss_uint64 csr = 0;
3962  static BitArrayRange R_csr_0 (31,20);
3963  etiss_uint64 csr_0 = R_csr_0.read(ba);
3964  csr += csr_0;
3965  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3966  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3967  partInit.getAffectedRegisters().add(reg_name[rd],64);
3968  partInit.getAffectedRegisters().add("instructionPointer",64);
3969  partInit.code() = std::string("//csrrs\n")+
3970  "etiss_uint32 temp = 0;\n"
3971  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3972  #if RISCV64_Pipeline1
3973  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3974  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3975  "etiss_uint32 num_stages = 4;\n"
3976  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3977  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3978  #endif
3979  #if RISCV64_Pipeline2
3980  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3981  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3982  "etiss_uint32 num_stages = 4;\n"
3983  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3984  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3985  #endif
3986 
3987  "etiss_uint64 xrs1 = 0;\n"
3988  "etiss_int64 mAddr = 0;\n"
3989  "etiss_int64 writeMask = 0;\n"
3990  "etiss_int64 writeMaskU = 0;\n"
3991  "etiss_int64 sAddr = 0;\n"
3992  "etiss_int64 writeMaskS = 0;\n"
3993  "etiss_int64 uAddr = 0;\n"
3994  "etiss_uint64 xrd = 0;\n"
3995  "etiss_int64 writeMaskM = 0;\n"
3996 
3997 "xrd = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
3998 #if RISCV64_DEBUG_CALL
3999 "printf(\"xrd = %#lx\\n\",xrd); \n"
4000 #endif
4001 "xrs1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
4002 #if RISCV64_DEBUG_CALL
4003 "printf(\"xrs1 = %#lx\\n\",xrs1); \n"
4004 #endif
4005 "if(" + toString(rd) + " != 0)\n"
4006 "{\n"
4007  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = xrd;\n"
4008  #if RISCV64_DEBUG_CALL
4009  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
4010  #endif
4011 "}\n"
4012 
4013 "if(" + toString(rs1) + " != 0)\n"
4014 "{\n"
4015  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
4016  "{\n"
4017  "uAddr = 0;\n"
4018  #if RISCV64_DEBUG_CALL
4019  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4020  #endif
4021  "sAddr = 256;\n"
4022  #if RISCV64_DEBUG_CALL
4023  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4024  #endif
4025  "mAddr = 768;\n"
4026  #if RISCV64_DEBUG_CALL
4027  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4028  #endif
4029  "writeMaskM = -9223372036846388805;\n"
4030  #if RISCV64_DEBUG_CALL
4031  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4032  #endif
4033  "writeMaskS = -9223372036853866189;\n"
4034  #if RISCV64_DEBUG_CALL
4035  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4036  #endif
4037  "writeMaskU = -9223372036853866479;\n"
4038  #if RISCV64_DEBUG_CALL
4039  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4040  #endif
4041  "}\n"
4042 
4043  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
4044  "{\n"
4045  "uAddr = 68;\n"
4046  #if RISCV64_DEBUG_CALL
4047  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4048  #endif
4049  "sAddr = 324;\n"
4050  #if RISCV64_DEBUG_CALL
4051  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4052  #endif
4053  "mAddr = 836;\n"
4054  #if RISCV64_DEBUG_CALL
4055  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4056  #endif
4057  "writeMaskM = 3003;\n"
4058  #if RISCV64_DEBUG_CALL
4059  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4060  #endif
4061  "writeMaskS = 819;\n"
4062  #if RISCV64_DEBUG_CALL
4063  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4064  #endif
4065  "writeMaskU = 273;\n"
4066  #if RISCV64_DEBUG_CALL
4067  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4068  #endif
4069  "}\n"
4070 
4071  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
4072  "{\n"
4073  "uAddr = 4;\n"
4074  #if RISCV64_DEBUG_CALL
4075  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4076  #endif
4077  "sAddr = 260;\n"
4078  #if RISCV64_DEBUG_CALL
4079  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4080  #endif
4081  "mAddr = 772;\n"
4082  #if RISCV64_DEBUG_CALL
4083  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4084  #endif
4085  "writeMaskM = 3003;\n"
4086  #if RISCV64_DEBUG_CALL
4087  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4088  #endif
4089  "writeMaskS = 819;\n"
4090  #if RISCV64_DEBUG_CALL
4091  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4092  #endif
4093  "writeMaskU = 273;\n"
4094  #if RISCV64_DEBUG_CALL
4095  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4096  #endif
4097  "}\n"
4098 
4099  "if(uAddr != sAddr)\n"
4100  "{\n"
4101  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
4102  "{\n"
4103  "writeMask = writeMaskM;\n"
4104  #if RISCV64_DEBUG_CALL
4105  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4106  #endif
4107  "}\n"
4108 
4109  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
4110  "{\n"
4111  "writeMask = writeMaskS;\n"
4112  #if RISCV64_DEBUG_CALL
4113  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4114  #endif
4115  "}\n"
4116 
4117  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
4118  "{\n"
4119  "writeMask = writeMaskU;\n"
4120  #if RISCV64_DEBUG_CALL
4121  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4122  #endif
4123  "}\n"
4124 
4125  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd | xrs1) & writeMask))&0xffffffffffffffff;\n"
4126  #if RISCV64_DEBUG_CALL
4127  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
4128  #endif
4129  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
4130  #if RISCV64_DEBUG_CALL
4131  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
4132  #endif
4133  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
4134  #if RISCV64_DEBUG_CALL
4135  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
4136  #endif
4137  "}\n"
4138 
4139  "else\n"
4140  "{\n"
4141  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (xrd | xrs1);\n"
4142  #if RISCV64_DEBUG_CALL
4143  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
4144  #endif
4145  "}\n"
4146 "}\n"
4147 
4148 
4149  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4150 
4151 ;
4152 return true;
4153 },
4154 0,
4155 nullptr
4156 );
4157 //-------------------------------------------------------------------------------------------------------------------
4158 static InstructionDefinition flw_rd_imm_xrs1_(
4159  ISA32_RISCV64,
4160  "flw",
4161  (uint32_t)0x2007,
4162  (uint32_t) 0x707f,
4163  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4164  {
4165  etiss_uint64 rs1 = 0;
4166  static BitArrayRange R_rs1_0 (19,15);
4167  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4168  rs1 += rs1_0;
4169  etiss_uint64 rd = 0;
4170  static BitArrayRange R_rd_0 (11,7);
4171  etiss_uint64 rd_0 = R_rd_0.read(ba);
4172  rd += rd_0;
4173  etiss_int64 imm = 0;
4174  static BitArrayRange R_imm_0 (31,20);
4175  etiss_int64 imm_0 = R_imm_0.read(ba);
4176  imm += imm_0;
4177  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4178  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4179  partInit.getAffectedRegisters().add(reg_name[rd],64);
4180  partInit.getAffectedRegisters().add("instructionPointer",64);
4181  partInit.code() = std::string("//flw\n")+
4182  "etiss_uint32 exception = 0;\n"
4183  "etiss_uint32 temp = 0;\n"
4184  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4185  #if RISCV64_Pipeline1
4186  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4187  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4188  "etiss_uint32 num_stages = 4;\n"
4189  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4190  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4191  #endif
4192  #if RISCV64_Pipeline2
4193  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4194  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4195  "etiss_uint32 num_stages = 4;\n"
4196  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4197  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4198  #endif
4199 
4200  "etiss_int64 offs = 0;\n"
4201  "etiss_int64 imm_extended = 0;\n"
4202  "etiss_uint32 res = 0;\n"
4203  "etiss_int64 upper = 0;\n"
4204 
4205 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4206 "{\n"
4207  "imm_extended = 0;\n"
4208  #if RISCV64_DEBUG_CALL
4209  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4210  #endif
4211 "}\n"
4212 
4213 "else\n"
4214 "{\n"
4215  "imm_extended = 4294967295;\n"
4216  #if RISCV64_DEBUG_CALL
4217  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4218  #endif
4219  "imm_extended = (imm_extended << 32);\n"
4220  #if RISCV64_DEBUG_CALL
4221  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4222  #endif
4223  "imm_extended = imm_extended + 4294963200;\n"
4224  #if RISCV64_DEBUG_CALL
4225  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4226  #endif
4227 "}\n"
4228 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4229 #if RISCV64_DEBUG_CALL
4230 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4231 #endif
4232 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
4233 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4234 "{\n"
4235  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4236 "}\n"
4237 "offs = (etiss_int64)cast_0 + imm_extended;\n"
4238 #if RISCV64_DEBUG_CALL
4239 "printf(\"offs = %#lx\\n\",offs); \n"
4240 #endif
4241  "etiss_uint32 MEM_offs;\n"
4242 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
4243 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
4244 "res = MEM_offs;\n"
4245 #if RISCV64_DEBUG_CALL
4246 "printf(\"res = %#x\\n\",res); \n"
4247 #endif
4248 "if(64 == 32)\n"
4249 "{\n"
4250  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
4251  #if RISCV64_DEBUG_CALL
4252  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
4253  #endif
4254 "}\n"
4255 
4256 "else\n"
4257 "{\n"
4258  "upper = - 1;\n"
4259  #if RISCV64_DEBUG_CALL
4260  "printf(\"upper = %#lx\\n\",upper); \n"
4261  #endif
4262  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
4263  #if RISCV64_DEBUG_CALL
4264  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
4265  #endif
4266 "}\n"
4267 
4268  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4269 
4270  "return exception;\n"
4271 ;
4272 return true;
4273 },
4274 0,
4275 nullptr
4276 );
4277 //-------------------------------------------------------------------------------------------------------------------
4278 static InstructionDefinition fsw_rs2_imm_xrs1_(
4279  ISA32_RISCV64,
4280  "fsw",
4281  (uint32_t)0x2027,
4282  (uint32_t) 0x707f,
4283  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4284  {
4285  etiss_uint64 rs2 = 0;
4286  static BitArrayRange R_rs2_0 (24,20);
4287  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
4288  rs2 += rs2_0;
4289  etiss_uint64 rs1 = 0;
4290  static BitArrayRange R_rs1_0 (19,15);
4291  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4292  rs1 += rs1_0;
4293  etiss_int64 imm = 0;
4294  static BitArrayRange R_imm_5 (31,25);
4295  etiss_int64 imm_5 = R_imm_5.read(ba);
4296  imm += imm_5<<5;
4297  static BitArrayRange R_imm_0 (11,7);
4298  etiss_int64 imm_0 = R_imm_0.read(ba);
4299  imm += imm_0;
4300  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4301  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4302  partInit.getRegisterDependencies().add(reg_name[rs2],64);
4303  partInit.getAffectedRegisters().add("instructionPointer",64);
4304  partInit.code() = std::string("//fsw\n")+
4305  "etiss_uint32 exception = 0;\n"
4306  "etiss_uint32 temp = 0;\n"
4307  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4308  #if RISCV64_Pipeline1
4309  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4310  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4311  "etiss_uint32 num_stages = 4;\n"
4312  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4313  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4314  #endif
4315  #if RISCV64_Pipeline2
4316  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4317  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4318  "etiss_uint32 num_stages = 4;\n"
4319  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4320  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4321  #endif
4322 
4323  "etiss_int64 offs = 0;\n"
4324  "etiss_int64 imm_extended = 0;\n"
4325 
4326 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4327 "{\n"
4328  "imm_extended = 0;\n"
4329  #if RISCV64_DEBUG_CALL
4330  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4331  #endif
4332 "}\n"
4333 
4334 "else\n"
4335 "{\n"
4336  "imm_extended = 4294967295;\n"
4337  #if RISCV64_DEBUG_CALL
4338  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4339  #endif
4340  "imm_extended = (imm_extended << 32);\n"
4341  #if RISCV64_DEBUG_CALL
4342  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4343  #endif
4344  "imm_extended = imm_extended + 4294963200;\n"
4345  #if RISCV64_DEBUG_CALL
4346  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4347  #endif
4348 "}\n"
4349 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4350 #if RISCV64_DEBUG_CALL
4351 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4352 #endif
4353 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
4354 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4355 "{\n"
4356  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4357 "}\n"
4358 "offs = (etiss_int64)cast_0 + imm_extended;\n"
4359 #if RISCV64_DEBUG_CALL
4360 "printf(\"offs = %#lx\\n\",offs); \n"
4361 #endif
4362  "etiss_uint32 MEM_offs;\n"
4363 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
4364 "MEM_offs = (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffff);\n"
4365 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
4366 #if RISCV64_DEBUG_CALL
4367 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
4368 #endif
4369 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
4370 "{\n"
4371  "((RISCV64*)cpu)->RES = 0;\n"
4372  #if RISCV64_DEBUG_CALL
4373  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
4374  #endif
4375 "}\n"
4376 
4377 
4378  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4379 
4380  "return exception;\n"
4381 ;
4382 return true;
4383 },
4384 0,
4385 nullptr
4386 );
4387 //-------------------------------------------------------------------------------------------------------------------
4388 static InstructionDefinition sltiu_rd_rs1_imm(
4389  ISA32_RISCV64,
4390  "sltiu",
4391  (uint32_t)0x3013,
4392  (uint32_t) 0x707f,
4393  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4394  {
4395  etiss_uint64 rs1 = 0;
4396  static BitArrayRange R_rs1_0 (19,15);
4397  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4398  rs1 += rs1_0;
4399  etiss_uint64 rd = 0;
4400  static BitArrayRange R_rd_0 (11,7);
4401  etiss_uint64 rd_0 = R_rd_0.read(ba);
4402  rd += rd_0;
4403  etiss_int64 imm = 0;
4404  static BitArrayRange R_imm_0 (31,20);
4405  etiss_int64 imm_0 = R_imm_0.read(ba);
4406  imm += imm_0;
4407  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4408  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4409  partInit.getAffectedRegisters().add(reg_name[rd],64);
4410  partInit.getAffectedRegisters().add("instructionPointer",64);
4411  partInit.code() = std::string("//sltiu\n")+
4412  "etiss_uint32 temp = 0;\n"
4413  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4414  #if RISCV64_Pipeline1
4415  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4416  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4417  "etiss_uint32 num_stages = 4;\n"
4418  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4419  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4420  #endif
4421  #if RISCV64_Pipeline2
4422  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4423  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4424  "etiss_uint32 num_stages = 4;\n"
4425  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4426  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4427  #endif
4428 
4429  "etiss_int64 imm_extended = 0;\n"
4430  "etiss_int64 full_imm = 0;\n"
4431  "etiss_int8 choose1 = 0;\n"
4432 
4433 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4434 "{\n"
4435  "imm_extended = 0;\n"
4436  #if RISCV64_DEBUG_CALL
4437  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4438  #endif
4439 "}\n"
4440 
4441 "else\n"
4442 "{\n"
4443  "imm_extended = 4294967295;\n"
4444  #if RISCV64_DEBUG_CALL
4445  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4446  #endif
4447  "imm_extended = (imm_extended << 32);\n"
4448  #if RISCV64_DEBUG_CALL
4449  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4450  #endif
4451  "imm_extended = imm_extended + 4294963200;\n"
4452  #if RISCV64_DEBUG_CALL
4453  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4454  #endif
4455 "}\n"
4456 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4457 #if RISCV64_DEBUG_CALL
4458 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4459 #endif
4460 "etiss_int64 cast_0 = imm_extended; \n"
4461 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4462 "{\n"
4463  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4464 "}\n"
4465 "full_imm = (etiss_int64)cast_0;\n"
4466 #if RISCV64_DEBUG_CALL
4467 "printf(\"full_imm = %#lx\\n\",full_imm); \n"
4468 #endif
4469 "if(" + toString(rd) + " != 0)\n"
4470 "{\n"
4471  "if((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "] < (etiss_uint64)full_imm)\n"
4472  "{\n"
4473  "choose1 = 1;\n"
4474  #if RISCV64_DEBUG_CALL
4475  "printf(\"choose1 = %#x\\n\",choose1); \n"
4476  #endif
4477  "}\n"
4478 
4479  "else\n"
4480  "{\n"
4481  "choose1 = 0;\n"
4482  #if RISCV64_DEBUG_CALL
4483  "printf(\"choose1 = %#x\\n\",choose1); \n"
4484  #endif
4485  "}\n"
4486  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = choose1;\n"
4487  #if RISCV64_DEBUG_CALL
4488  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
4489  #endif
4490 "}\n"
4491 
4492 
4493  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4494 
4495 ;
4496 return true;
4497 },
4498 0,
4499 nullptr
4500 );
4501 //-------------------------------------------------------------------------------------------------------------------
4502 static InstructionDefinition csrrc_rd_csr_rs1(
4503  ISA32_RISCV64,
4504  "csrrc",
4505  (uint32_t)0x3073,
4506  (uint32_t) 0x707f,
4507  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4508  {
4509  etiss_uint64 rs1 = 0;
4510  static BitArrayRange R_rs1_0 (19,15);
4511  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4512  rs1 += rs1_0;
4513  etiss_uint64 rd = 0;
4514  static BitArrayRange R_rd_0 (11,7);
4515  etiss_uint64 rd_0 = R_rd_0.read(ba);
4516  rd += rd_0;
4517  etiss_uint64 csr = 0;
4518  static BitArrayRange R_csr_0 (31,20);
4519  etiss_uint64 csr_0 = R_csr_0.read(ba);
4520  csr += csr_0;
4521  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4522  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4523  partInit.getAffectedRegisters().add(reg_name[rd],64);
4524  partInit.getAffectedRegisters().add("instructionPointer",64);
4525  partInit.code() = std::string("//csrrc\n")+
4526  "etiss_uint32 temp = 0;\n"
4527  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4528  #if RISCV64_Pipeline1
4529  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4530  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4531  "etiss_uint32 num_stages = 4;\n"
4532  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4533  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4534  #endif
4535  #if RISCV64_Pipeline2
4536  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4537  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4538  "etiss_uint32 num_stages = 4;\n"
4539  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4540  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4541  #endif
4542 
4543  "etiss_uint64 xrs1 = 0;\n"
4544  "etiss_int64 mAddr = 0;\n"
4545  "etiss_int64 writeMask = 0;\n"
4546  "etiss_int64 writeMaskU = 0;\n"
4547  "etiss_int64 sAddr = 0;\n"
4548  "etiss_int64 writeMaskS = 0;\n"
4549  "etiss_int64 uAddr = 0;\n"
4550  "etiss_uint64 xrd = 0;\n"
4551  "etiss_int64 writeMaskM = 0;\n"
4552 
4553 "xrd = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
4554 #if RISCV64_DEBUG_CALL
4555 "printf(\"xrd = %#lx\\n\",xrd); \n"
4556 #endif
4557 "xrs1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
4558 #if RISCV64_DEBUG_CALL
4559 "printf(\"xrs1 = %#lx\\n\",xrs1); \n"
4560 #endif
4561 "if(" + toString(rd) + " != 0)\n"
4562 "{\n"
4563  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = xrd;\n"
4564  #if RISCV64_DEBUG_CALL
4565  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
4566  #endif
4567 "}\n"
4568 
4569 "if(" + toString(rs1) + " != 0)\n"
4570 "{\n"
4571  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
4572  "{\n"
4573  "uAddr = 0;\n"
4574  #if RISCV64_DEBUG_CALL
4575  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4576  #endif
4577  "sAddr = 256;\n"
4578  #if RISCV64_DEBUG_CALL
4579  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4580  #endif
4581  "mAddr = 768;\n"
4582  #if RISCV64_DEBUG_CALL
4583  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4584  #endif
4585  "writeMaskM = -9223372036846388805;\n"
4586  #if RISCV64_DEBUG_CALL
4587  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4588  #endif
4589  "writeMaskS = -9223372036853866189;\n"
4590  #if RISCV64_DEBUG_CALL
4591  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4592  #endif
4593  "writeMaskU = -9223372036853866479;\n"
4594  #if RISCV64_DEBUG_CALL
4595  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4596  #endif
4597  "}\n"
4598 
4599  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
4600  "{\n"
4601  "uAddr = 68;\n"
4602  #if RISCV64_DEBUG_CALL
4603  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4604  #endif
4605  "sAddr = 324;\n"
4606  #if RISCV64_DEBUG_CALL
4607  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4608  #endif
4609  "mAddr = 836;\n"
4610  #if RISCV64_DEBUG_CALL
4611  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4612  #endif
4613  "writeMaskM = 3003;\n"
4614  #if RISCV64_DEBUG_CALL
4615  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4616  #endif
4617  "writeMaskS = 819;\n"
4618  #if RISCV64_DEBUG_CALL
4619  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4620  #endif
4621  "writeMaskU = 273;\n"
4622  #if RISCV64_DEBUG_CALL
4623  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4624  #endif
4625  "}\n"
4626 
4627  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
4628  "{\n"
4629  "uAddr = 4;\n"
4630  #if RISCV64_DEBUG_CALL
4631  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4632  #endif
4633  "sAddr = 260;\n"
4634  #if RISCV64_DEBUG_CALL
4635  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4636  #endif
4637  "mAddr = 772;\n"
4638  #if RISCV64_DEBUG_CALL
4639  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4640  #endif
4641  "writeMaskM = 3003;\n"
4642  #if RISCV64_DEBUG_CALL
4643  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4644  #endif
4645  "writeMaskS = 819;\n"
4646  #if RISCV64_DEBUG_CALL
4647  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4648  #endif
4649  "writeMaskU = 273;\n"
4650  #if RISCV64_DEBUG_CALL
4651  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4652  #endif
4653  "}\n"
4654 
4655  "if(uAddr != sAddr)\n"
4656  "{\n"
4657  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
4658  "{\n"
4659  "writeMask = writeMaskM;\n"
4660  #if RISCV64_DEBUG_CALL
4661  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4662  #endif
4663  "}\n"
4664 
4665  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
4666  "{\n"
4667  "writeMask = writeMaskS;\n"
4668  #if RISCV64_DEBUG_CALL
4669  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4670  #endif
4671  "}\n"
4672 
4673  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
4674  "{\n"
4675  "writeMask = writeMaskU;\n"
4676  #if RISCV64_DEBUG_CALL
4677  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4678  #endif
4679  "}\n"
4680 
4681  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd & ~xrs1) & writeMask))&0xffffffffffffffff&0xffffffffffffffff;\n"
4682  #if RISCV64_DEBUG_CALL
4683  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
4684  #endif
4685  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
4686  #if RISCV64_DEBUG_CALL
4687  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
4688  #endif
4689  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
4690  #if RISCV64_DEBUG_CALL
4691  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
4692  #endif
4693  "}\n"
4694 
4695  "else\n"
4696  "{\n"
4697  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (xrd & ~xrs1)&0xffffffffffffffff;\n"
4698  #if RISCV64_DEBUG_CALL
4699  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
4700  #endif
4701  "}\n"
4702 "}\n"
4703 
4704 
4705  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4706 
4707 ;
4708 return true;
4709 },
4710 0,
4711 nullptr
4712 );
4713 //-------------------------------------------------------------------------------------------------------------------
4714 static InstructionDefinition ld_rd_imm_rs1_(
4715  ISA32_RISCV64,
4716  "ld",
4717  (uint32_t)0x3003,
4718  (uint32_t) 0x707f,
4719  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4720  {
4721  etiss_uint64 rs1 = 0;
4722  static BitArrayRange R_rs1_0 (19,15);
4723  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4724  rs1 += rs1_0;
4725  etiss_uint64 rd = 0;
4726  static BitArrayRange R_rd_0 (11,7);
4727  etiss_uint64 rd_0 = R_rd_0.read(ba);
4728  rd += rd_0;
4729  etiss_int64 imm = 0;
4730  static BitArrayRange R_imm_0 (31,20);
4731  etiss_int64 imm_0 = R_imm_0.read(ba);
4732  imm += imm_0;
4733  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4734  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4735  partInit.getAffectedRegisters().add(reg_name[rd],64);
4736  partInit.getAffectedRegisters().add("instructionPointer",64);
4737  partInit.code() = std::string("//ld\n")+
4738  "etiss_uint32 exception = 0;\n"
4739  "etiss_uint32 temp = 0;\n"
4740  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4741  #if RISCV64_Pipeline1
4742  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4743  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4744  "etiss_uint32 num_stages = 4;\n"
4745  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4746  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4747  #endif
4748  #if RISCV64_Pipeline2
4749  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4750  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4751  "etiss_uint32 num_stages = 4;\n"
4752  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4753  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4754  #endif
4755 
4756  "etiss_int64 offs = 0;\n"
4757  "etiss_int64 imm_extended = 0;\n"
4758 
4759 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4760 "{\n"
4761  "imm_extended = 0;\n"
4762  #if RISCV64_DEBUG_CALL
4763  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4764  #endif
4765 "}\n"
4766 
4767 "else\n"
4768 "{\n"
4769  "imm_extended = 4294967295;\n"
4770  #if RISCV64_DEBUG_CALL
4771  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4772  #endif
4773  "imm_extended = (imm_extended << 32);\n"
4774  #if RISCV64_DEBUG_CALL
4775  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4776  #endif
4777  "imm_extended = imm_extended + 4294963200;\n"
4778  #if RISCV64_DEBUG_CALL
4779  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4780  #endif
4781 "}\n"
4782 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4783 #if RISCV64_DEBUG_CALL
4784 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4785 #endif
4786 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
4787 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4788 "{\n"
4789  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4790 "}\n"
4791 "offs = (etiss_int64)cast_0 + imm_extended;\n"
4792 #if RISCV64_DEBUG_CALL
4793 "printf(\"offs = %#lx\\n\",offs); \n"
4794 #endif
4795 "if(" + toString(rd) + " != 0)\n"
4796 "{\n"
4797  "etiss_uint64 MEM_offs;\n"
4798  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
4799  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
4800  "etiss_int64 cast_1 = MEM_offs; \n"
4801  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
4802  "{\n"
4803  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
4804  "}\n"
4805  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
4806  #if RISCV64_DEBUG_CALL
4807  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
4808  #endif
4809 "}\n"
4810 
4811 
4812  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4813 
4814  "return exception;\n"
4815 ;
4816 return true;
4817 },
4818 0,
4819 nullptr
4820 );
4821 //-------------------------------------------------------------------------------------------------------------------
4822 static InstructionDefinition sd_rs2_imm_rs1_(
4823  ISA32_RISCV64,
4824  "sd",
4825  (uint32_t)0x3023,
4826  (uint32_t) 0x707f,
4827  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4828  {
4829  etiss_uint64 rs2 = 0;
4830  static BitArrayRange R_rs2_0 (24,20);
4831  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
4832  rs2 += rs2_0;
4833  etiss_uint64 rs1 = 0;
4834  static BitArrayRange R_rs1_0 (19,15);
4835  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4836  rs1 += rs1_0;
4837  etiss_int64 imm = 0;
4838  static BitArrayRange R_imm_5 (31,25);
4839  etiss_int64 imm_5 = R_imm_5.read(ba);
4840  imm += imm_5<<5;
4841  static BitArrayRange R_imm_0 (11,7);
4842  etiss_int64 imm_0 = R_imm_0.read(ba);
4843  imm += imm_0;
4844  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4845  partInit.getRegisterDependencies().add(reg_name[rs2],64);
4846  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4847  partInit.getAffectedRegisters().add("instructionPointer",64);
4848  partInit.code() = std::string("//sd\n")+
4849  "etiss_uint32 exception = 0;\n"
4850  "etiss_uint32 temp = 0;\n"
4851  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4852  #if RISCV64_Pipeline1
4853  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4854  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4855  "etiss_uint32 num_stages = 4;\n"
4856  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4857  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4858  #endif
4859  #if RISCV64_Pipeline2
4860  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4861  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4862  "etiss_uint32 num_stages = 4;\n"
4863  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4864  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4865  #endif
4866 
4867  "etiss_int64 offs = 0;\n"
4868  "etiss_int64 imm_extended = 0;\n"
4869 
4870 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4871 "{\n"
4872  "imm_extended = 0;\n"
4873  #if RISCV64_DEBUG_CALL
4874  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4875  #endif
4876 "}\n"
4877 
4878 "else\n"
4879 "{\n"
4880  "imm_extended = 4294967295;\n"
4881  #if RISCV64_DEBUG_CALL
4882  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4883  #endif
4884  "imm_extended = (imm_extended << 32);\n"
4885  #if RISCV64_DEBUG_CALL
4886  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4887  #endif
4888  "imm_extended = imm_extended + 4294963200;\n"
4889  #if RISCV64_DEBUG_CALL
4890  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4891  #endif
4892 "}\n"
4893 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4894 #if RISCV64_DEBUG_CALL
4895 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4896 #endif
4897 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
4898 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4899 "{\n"
4900  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4901 "}\n"
4902 "offs = (etiss_int64)cast_0 + imm_extended;\n"
4903 #if RISCV64_DEBUG_CALL
4904 "printf(\"offs = %#lx\\n\",offs); \n"
4905 #endif
4906  "etiss_uint64 MEM_offs;\n"
4907 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
4908 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
4909 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
4910 #if RISCV64_DEBUG_CALL
4911 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
4912 #endif
4913 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
4914 "{\n"
4915  "((RISCV64*)cpu)->RES = 0;\n"
4916  #if RISCV64_DEBUG_CALL
4917  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
4918  #endif
4919 "}\n"
4920 
4921 
4922  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4923 
4924  "return exception;\n"
4925 ;
4926 return true;
4927 },
4928 0,
4929 nullptr
4930 );
4931 //-------------------------------------------------------------------------------------------------------------------
4932 static InstructionDefinition fld_rd_imm_rs1_(
4933  ISA32_RISCV64,
4934  "fld",
4935  (uint32_t)0x3007,
4936  (uint32_t) 0x707f,
4937  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4938  {
4939  etiss_uint64 rs1 = 0;
4940  static BitArrayRange R_rs1_0 (19,15);
4941  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4942  rs1 += rs1_0;
4943  etiss_uint64 rd = 0;
4944  static BitArrayRange R_rd_0 (11,7);
4945  etiss_uint64 rd_0 = R_rd_0.read(ba);
4946  rd += rd_0;
4947  etiss_int64 imm = 0;
4948  static BitArrayRange R_imm_0 (31,20);
4949  etiss_int64 imm_0 = R_imm_0.read(ba);
4950  imm += imm_0;
4951  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4952  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4953  partInit.getAffectedRegisters().add(reg_name[rd],64);
4954  partInit.getAffectedRegisters().add("instructionPointer",64);
4955  partInit.code() = std::string("//fld\n")+
4956  "etiss_uint32 exception = 0;\n"
4957  "etiss_uint32 temp = 0;\n"
4958  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4959  #if RISCV64_Pipeline1
4960  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4961  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4962  "etiss_uint32 num_stages = 4;\n"
4963  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4964  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4965  #endif
4966  #if RISCV64_Pipeline2
4967  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4968  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4969  "etiss_uint32 num_stages = 4;\n"
4970  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4971  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4972  #endif
4973 
4974  "etiss_int64 offs = 0;\n"
4975  "etiss_int64 imm_extended = 0;\n"
4976  "etiss_uint64 res = 0;\n"
4977  "etiss_int64 upper = 0;\n"
4978 
4979 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4980 "{\n"
4981  "imm_extended = 0;\n"
4982  #if RISCV64_DEBUG_CALL
4983  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4984  #endif
4985 "}\n"
4986 
4987 "else\n"
4988 "{\n"
4989  "imm_extended = 4294967295;\n"
4990  #if RISCV64_DEBUG_CALL
4991  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4992  #endif
4993  "imm_extended = (imm_extended << 32);\n"
4994  #if RISCV64_DEBUG_CALL
4995  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4996  #endif
4997  "imm_extended = imm_extended + 4294963200;\n"
4998  #if RISCV64_DEBUG_CALL
4999  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5000  #endif
5001 "}\n"
5002 "imm_extended = imm_extended + " + toString(imm) + ";\n"
5003 #if RISCV64_DEBUG_CALL
5004 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5005 #endif
5006 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
5007 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
5008 "{\n"
5009  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
5010 "}\n"
5011 "offs = (etiss_int64)cast_0 + imm_extended;\n"
5012 #if RISCV64_DEBUG_CALL
5013 "printf(\"offs = %#lx\\n\",offs); \n"
5014 #endif
5015  "etiss_uint64 MEM_offs;\n"
5016 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
5017 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
5018 "res = MEM_offs;\n"
5019 #if RISCV64_DEBUG_CALL
5020 "printf(\"res = %#lx\\n\",res); \n"
5021 #endif
5022 "if(64 == 64)\n"
5023 "{\n"
5024  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
5025  #if RISCV64_DEBUG_CALL
5026  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5027  #endif
5028 "}\n"
5029 
5030 "else\n"
5031 "{\n"
5032  "upper = - 1;\n"
5033  #if RISCV64_DEBUG_CALL
5034  "printf(\"upper = %#lx\\n\",upper); \n"
5035  #endif
5036  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
5037  #if RISCV64_DEBUG_CALL
5038  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5039  #endif
5040 "}\n"
5041 
5042  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5043 
5044  "return exception;\n"
5045 ;
5046 return true;
5047 },
5048 0,
5049 nullptr
5050 );
5051 //-------------------------------------------------------------------------------------------------------------------
5052 static InstructionDefinition fsd_rs2_imm_rs1_(
5053  ISA32_RISCV64,
5054  "fsd",
5055  (uint32_t)0x3027,
5056  (uint32_t) 0x707f,
5057  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5058  {
5059  etiss_uint64 rs2 = 0;
5060  static BitArrayRange R_rs2_0 (24,20);
5061  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5062  rs2 += rs2_0;
5063  etiss_uint64 rs1 = 0;
5064  static BitArrayRange R_rs1_0 (19,15);
5065  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5066  rs1 += rs1_0;
5067  etiss_int64 imm = 0;
5068  static BitArrayRange R_imm_5 (31,25);
5069  etiss_int64 imm_5 = R_imm_5.read(ba);
5070  imm += imm_5<<5;
5071  static BitArrayRange R_imm_0 (11,7);
5072  etiss_int64 imm_0 = R_imm_0.read(ba);
5073  imm += imm_0;
5074  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5075  partInit.getRegisterDependencies().add(reg_name[rs1],64);
5076  partInit.getRegisterDependencies().add(reg_name[rs2],64);
5077  partInit.getAffectedRegisters().add("instructionPointer",64);
5078  partInit.code() = std::string("//fsd\n")+
5079  "etiss_uint32 exception = 0;\n"
5080  "etiss_uint32 temp = 0;\n"
5081  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5082  #if RISCV64_Pipeline1
5083  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5084  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5085  "etiss_uint32 num_stages = 4;\n"
5086  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5087  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5088  #endif
5089  #if RISCV64_Pipeline2
5090  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5091  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5092  "etiss_uint32 num_stages = 4;\n"
5093  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5094  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5095  #endif
5096 
5097  "etiss_int64 offs = 0;\n"
5098  "etiss_int64 imm_extended = 0;\n"
5099 
5100 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
5101 "{\n"
5102  "imm_extended = 0;\n"
5103  #if RISCV64_DEBUG_CALL
5104  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
5105  #endif
5106 "}\n"
5107 
5108 "else\n"
5109 "{\n"
5110  "imm_extended = 4294967295;\n"
5111  #if RISCV64_DEBUG_CALL
5112  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
5113  #endif
5114  "imm_extended = (imm_extended << 32);\n"
5115  #if RISCV64_DEBUG_CALL
5116  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5117  #endif
5118  "imm_extended = imm_extended + 4294963200;\n"
5119  #if RISCV64_DEBUG_CALL
5120  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5121  #endif
5122 "}\n"
5123 "imm_extended = imm_extended + " + toString(imm) + ";\n"
5124 #if RISCV64_DEBUG_CALL
5125 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5126 #endif
5127 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
5128 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
5129 "{\n"
5130  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
5131 "}\n"
5132 "offs = (etiss_int64)cast_0 + imm_extended;\n"
5133 #if RISCV64_DEBUG_CALL
5134 "printf(\"offs = %#lx\\n\",offs); \n"
5135 #endif
5136  "etiss_uint64 MEM_offs;\n"
5137 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
5138 "MEM_offs = (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff);\n"
5139 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
5140 #if RISCV64_DEBUG_CALL
5141 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
5142 #endif
5143 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
5144 "{\n"
5145  "((RISCV64*)cpu)->RES = 0;\n"
5146  #if RISCV64_DEBUG_CALL
5147  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
5148  #endif
5149 "}\n"
5150 
5151 
5152  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5153 
5154  "return exception;\n"
5155 ;
5156 return true;
5157 },
5158 0,
5159 nullptr
5160 );
5161 //-------------------------------------------------------------------------------------------------------------------
5162 static InstructionDefinition fmadd_s_rd_frs1_frs2_frs3(
5163  ISA32_RISCV64,
5164  "fmadd.s",
5165  (uint32_t)0x43,
5166  (uint32_t) 0x600007f,
5167  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5168  {
5169  etiss_uint64 rs2 = 0;
5170  static BitArrayRange R_rs2_0 (24,20);
5171  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5172  rs2 += rs2_0;
5173  etiss_uint64 rs1 = 0;
5174  static BitArrayRange R_rs1_0 (19,15);
5175  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5176  rs1 += rs1_0;
5177  etiss_uint64 rd = 0;
5178  static BitArrayRange R_rd_0 (11,7);
5179  etiss_uint64 rd_0 = R_rd_0.read(ba);
5180  rd += rd_0;
5181  etiss_uint64 rs3 = 0;
5182  static BitArrayRange R_rs3_0 (31,27);
5183  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5184  rs3 += rs3_0;
5185  etiss_uint64 rm = 0;
5186  static BitArrayRange R_rm_0 (14,12);
5187  etiss_uint64 rm_0 = R_rm_0.read(ba);
5188  rm += rm_0;
5189  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5190  partInit.getAffectedRegisters().add(reg_name[rd],64);
5191  partInit.getAffectedRegisters().add("instructionPointer",64);
5192  partInit.code() = std::string("//fmadd.s\n")+
5193  "etiss_uint32 temp = 0;\n"
5194  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5195  #if RISCV64_Pipeline1
5196  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5197  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5198  "etiss_uint32 num_stages = 4;\n"
5199  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5200  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5201  #endif
5202  #if RISCV64_Pipeline2
5203  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5204  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5205  "etiss_uint32 num_stages = 4;\n"
5206  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5207  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5208  #endif
5209 
5210  "etiss_uint32 res = 0;\n"
5211  "etiss_int64 upper = 0;\n"
5212  "etiss_uint32 flags = 0;\n"
5213  "etiss_uint32 frs1 = 0;\n"
5214  "etiss_uint32 choose1 = 0;\n"
5215  "etiss_uint32 frs2 = 0;\n"
5216  "etiss_uint32 frs3 = 0;\n"
5217 
5218 "if(64 == 32)\n"
5219 "{\n"
5220  "if(" + toString(rm) + " < 7)\n"
5221  "{\n"
5222  "choose1 = (" + toString(rm) + " & 0xff);\n"
5223  #if RISCV64_DEBUG_CALL
5224  "printf(\"choose1 = %#x\\n\",choose1); \n"
5225  #endif
5226  "}\n"
5227 
5228  "else\n"
5229  "{\n"
5230  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5231  #if RISCV64_DEBUG_CALL
5232  "printf(\"choose1 = %#x\\n\",choose1); \n"
5233  #endif
5234  "}\n"
5235  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], ((RISCV64*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)0, choose1);\n"
5236  #if RISCV64_DEBUG_CALL
5237  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5238  #endif
5239 "}\n"
5240 
5241 "else\n"
5242 "{\n"
5243  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
5244  #if RISCV64_DEBUG_CALL
5245  "printf(\"frs1 = %#x\\n\",frs1); \n"
5246  #endif
5247  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
5248  #if RISCV64_DEBUG_CALL
5249  "printf(\"frs2 = %#x\\n\",frs2); \n"
5250  #endif
5251  "frs3 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs3) + "]);\n"
5252  #if RISCV64_DEBUG_CALL
5253  "printf(\"frs3 = %#x\\n\",frs3); \n"
5254  #endif
5255  "if(" + toString(rm) + " < 7)\n"
5256  "{\n"
5257  "choose1 = (" + toString(rm) + " & 0xff);\n"
5258  #if RISCV64_DEBUG_CALL
5259  "printf(\"choose1 = %#x\\n\",choose1); \n"
5260  #endif
5261  "}\n"
5262 
5263  "else\n"
5264  "{\n"
5265  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5266  #if RISCV64_DEBUG_CALL
5267  "printf(\"choose1 = %#x\\n\",choose1); \n"
5268  #endif
5269  "}\n"
5270  "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)0, choose1);\n"
5271  #if RISCV64_DEBUG_CALL
5272  "printf(\"res = %#x\\n\",res); \n"
5273  #endif
5274  "upper = - 1;\n"
5275  #if RISCV64_DEBUG_CALL
5276  "printf(\"upper = %#lx\\n\",upper); \n"
5277  #endif
5278  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
5279  #if RISCV64_DEBUG_CALL
5280  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5281  #endif
5282 "}\n"
5283 "flags = fget_flags();\n"
5284 #if RISCV64_DEBUG_CALL
5285 "printf(\"flags = %#x\\n\",flags); \n"
5286 #endif
5287 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5288 #if RISCV64_DEBUG_CALL
5289 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5290 #endif
5291 
5292  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5293 
5294 ;
5295 return true;
5296 },
5297 0,
5298 nullptr
5299 );
5300 //-------------------------------------------------------------------------------------------------------------------
5301 static InstructionDefinition fmsub_s_rd_frs1_frs2_frs3(
5302  ISA32_RISCV64,
5303  "fmsub.s",
5304  (uint32_t)0x47,
5305  (uint32_t) 0x600007f,
5306  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5307  {
5308  etiss_uint64 rs2 = 0;
5309  static BitArrayRange R_rs2_0 (24,20);
5310  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5311  rs2 += rs2_0;
5312  etiss_uint64 rs1 = 0;
5313  static BitArrayRange R_rs1_0 (19,15);
5314  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5315  rs1 += rs1_0;
5316  etiss_uint64 rd = 0;
5317  static BitArrayRange R_rd_0 (11,7);
5318  etiss_uint64 rd_0 = R_rd_0.read(ba);
5319  rd += rd_0;
5320  etiss_uint64 rs3 = 0;
5321  static BitArrayRange R_rs3_0 (31,27);
5322  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5323  rs3 += rs3_0;
5324  etiss_uint64 rm = 0;
5325  static BitArrayRange R_rm_0 (14,12);
5326  etiss_uint64 rm_0 = R_rm_0.read(ba);
5327  rm += rm_0;
5328  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5329  partInit.getAffectedRegisters().add(reg_name[rd],64);
5330  partInit.getAffectedRegisters().add("instructionPointer",64);
5331  partInit.code() = std::string("//fmsub.s\n")+
5332  "etiss_uint32 temp = 0;\n"
5333  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5334  #if RISCV64_Pipeline1
5335  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5336  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5337  "etiss_uint32 num_stages = 4;\n"
5338  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5339  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5340  #endif
5341  #if RISCV64_Pipeline2
5342  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5343  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5344  "etiss_uint32 num_stages = 4;\n"
5345  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5346  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5347  #endif
5348 
5349  "etiss_uint32 res = 0;\n"
5350  "etiss_int64 upper = 0;\n"
5351  "etiss_uint32 flags = 0;\n"
5352  "etiss_uint32 frs1 = 0;\n"
5353  "etiss_uint32 choose1 = 0;\n"
5354  "etiss_uint32 frs2 = 0;\n"
5355  "etiss_uint32 frs3 = 0;\n"
5356 
5357 "if(64 == 32)\n"
5358 "{\n"
5359  "if(" + toString(rm) + " < 7)\n"
5360  "{\n"
5361  "choose1 = (" + toString(rm) + " & 0xff);\n"
5362  #if RISCV64_DEBUG_CALL
5363  "printf(\"choose1 = %#x\\n\",choose1); \n"
5364  #endif
5365  "}\n"
5366 
5367  "else\n"
5368  "{\n"
5369  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5370  #if RISCV64_DEBUG_CALL
5371  "printf(\"choose1 = %#x\\n\",choose1); \n"
5372  #endif
5373  "}\n"
5374  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], ((RISCV64*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)1, choose1);\n"
5375  #if RISCV64_DEBUG_CALL
5376  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5377  #endif
5378 "}\n"
5379 
5380 "else\n"
5381 "{\n"
5382  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
5383  #if RISCV64_DEBUG_CALL
5384  "printf(\"frs1 = %#x\\n\",frs1); \n"
5385  #endif
5386  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
5387  #if RISCV64_DEBUG_CALL
5388  "printf(\"frs2 = %#x\\n\",frs2); \n"
5389  #endif
5390  "frs3 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs3) + "]);\n"
5391  #if RISCV64_DEBUG_CALL
5392  "printf(\"frs3 = %#x\\n\",frs3); \n"
5393  #endif
5394  "if(" + toString(rm) + " < 7)\n"
5395  "{\n"
5396  "choose1 = (" + toString(rm) + " & 0xff);\n"
5397  #if RISCV64_DEBUG_CALL
5398  "printf(\"choose1 = %#x\\n\",choose1); \n"
5399  #endif
5400  "}\n"
5401 
5402  "else\n"
5403  "{\n"
5404  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5405  #if RISCV64_DEBUG_CALL
5406  "printf(\"choose1 = %#x\\n\",choose1); \n"
5407  #endif
5408  "}\n"
5409  "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)1, choose1);\n"
5410  #if RISCV64_DEBUG_CALL
5411  "printf(\"res = %#x\\n\",res); \n"
5412  #endif
5413  "upper = - 1;\n"
5414  #if RISCV64_DEBUG_CALL
5415  "printf(\"upper = %#lx\\n\",upper); \n"
5416  #endif
5417  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
5418  #if RISCV64_DEBUG_CALL
5419  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5420  #endif
5421 "}\n"
5422 "flags = fget_flags();\n"
5423 #if RISCV64_DEBUG_CALL
5424 "printf(\"flags = %#x\\n\",flags); \n"
5425 #endif
5426 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5427 #if RISCV64_DEBUG_CALL
5428 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5429 #endif
5430 
5431  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5432 
5433 ;
5434 return true;
5435 },
5436 0,
5437 nullptr
5438 );
5439 //-------------------------------------------------------------------------------------------------------------------
5440 static InstructionDefinition fnmadd_s_rd_frs1_frs2_frs3(
5441  ISA32_RISCV64,
5442  "fnmadd.s",
5443  (uint32_t)0x4f,
5444  (uint32_t) 0x600007f,
5445  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5446  {
5447  etiss_uint64 rs2 = 0;
5448  static BitArrayRange R_rs2_0 (24,20);
5449  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5450  rs2 += rs2_0;
5451  etiss_uint64 rs1 = 0;
5452  static BitArrayRange R_rs1_0 (19,15);
5453  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5454  rs1 += rs1_0;
5455  etiss_uint64 rd = 0;
5456  static BitArrayRange R_rd_0 (11,7);
5457  etiss_uint64 rd_0 = R_rd_0.read(ba);
5458  rd += rd_0;
5459  etiss_uint64 rs3 = 0;
5460  static BitArrayRange R_rs3_0 (31,27);
5461  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5462  rs3 += rs3_0;
5463  etiss_uint64 rm = 0;
5464  static BitArrayRange R_rm_0 (14,12);
5465  etiss_uint64 rm_0 = R_rm_0.read(ba);
5466  rm += rm_0;
5467  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5468  partInit.getAffectedRegisters().add(reg_name[rd],64);
5469  partInit.getAffectedRegisters().add("instructionPointer",64);
5470  partInit.code() = std::string("//fnmadd.s\n")+
5471  "etiss_uint32 temp = 0;\n"
5472  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5473  #if RISCV64_Pipeline1
5474  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5475  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5476  "etiss_uint32 num_stages = 4;\n"
5477  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5478  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5479  #endif
5480  #if RISCV64_Pipeline2
5481  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5482  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5483  "etiss_uint32 num_stages = 4;\n"
5484  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5485  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5486  #endif
5487 
5488  "etiss_uint32 res = 0;\n"
5489  "etiss_int64 upper = 0;\n"
5490  "etiss_uint32 flags = 0;\n"
5491  "etiss_uint32 frs1 = 0;\n"
5492  "etiss_uint32 choose1 = 0;\n"
5493  "etiss_uint32 frs2 = 0;\n"
5494  "etiss_uint32 frs3 = 0;\n"
5495 
5496 "if(64 == 32)\n"
5497 "{\n"
5498  "if(" + toString(rm) + " < 7)\n"
5499  "{\n"
5500  "choose1 = (" + toString(rm) + " & 0xff);\n"
5501  #if RISCV64_DEBUG_CALL
5502  "printf(\"choose1 = %#x\\n\",choose1); \n"
5503  #endif
5504  "}\n"
5505 
5506  "else\n"
5507  "{\n"
5508  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5509  #if RISCV64_DEBUG_CALL
5510  "printf(\"choose1 = %#x\\n\",choose1); \n"
5511  #endif
5512  "}\n"
5513  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], ((RISCV64*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)2, choose1);\n"
5514  #if RISCV64_DEBUG_CALL
5515  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5516  #endif
5517 "}\n"
5518 
5519 "else\n"
5520 "{\n"
5521  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
5522  #if RISCV64_DEBUG_CALL
5523  "printf(\"frs1 = %#x\\n\",frs1); \n"
5524  #endif
5525  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
5526  #if RISCV64_DEBUG_CALL
5527  "printf(\"frs2 = %#x\\n\",frs2); \n"
5528  #endif
5529  "frs3 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs3) + "]);\n"
5530  #if RISCV64_DEBUG_CALL
5531  "printf(\"frs3 = %#x\\n\",frs3); \n"
5532  #endif
5533  "if(" + toString(rm) + " < 7)\n"
5534  "{\n"
5535  "choose1 = (" + toString(rm) + " & 0xff);\n"
5536  #if RISCV64_DEBUG_CALL
5537  "printf(\"choose1 = %#x\\n\",choose1); \n"
5538  #endif
5539  "}\n"
5540 
5541  "else\n"
5542  "{\n"
5543  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5544  #if RISCV64_DEBUG_CALL
5545  "printf(\"choose1 = %#x\\n\",choose1); \n"
5546  #endif
5547  "}\n"
5548  "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)2, choose1);\n"
5549  #if RISCV64_DEBUG_CALL
5550  "printf(\"res = %#x\\n\",res); \n"
5551  #endif
5552  "upper = - 1;\n"
5553  #if RISCV64_DEBUG_CALL
5554  "printf(\"upper = %#lx\\n\",upper); \n"
5555  #endif
5556  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
5557  #if RISCV64_DEBUG_CALL
5558  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5559  #endif
5560 "}\n"
5561 "flags = fget_flags();\n"
5562 #if RISCV64_DEBUG_CALL
5563 "printf(\"flags = %#x\\n\",flags); \n"
5564 #endif
5565 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5566 #if RISCV64_DEBUG_CALL
5567 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5568 #endif
5569 
5570  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5571 
5572 ;
5573 return true;
5574 },
5575 0,
5576 nullptr
5577 );
5578 //-------------------------------------------------------------------------------------------------------------------
5579 static InstructionDefinition fnmsub_s_rd_frs1_frs2_frs3(
5580  ISA32_RISCV64,
5581  "fnmsub.s",
5582  (uint32_t)0x4b,
5583  (uint32_t) 0x600007f,
5584  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5585  {
5586  etiss_uint64 rs2 = 0;
5587  static BitArrayRange R_rs2_0 (24,20);
5588  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5589  rs2 += rs2_0;
5590  etiss_uint64 rs1 = 0;
5591  static BitArrayRange R_rs1_0 (19,15);
5592  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5593  rs1 += rs1_0;
5594  etiss_uint64 rd = 0;
5595  static BitArrayRange R_rd_0 (11,7);
5596  etiss_uint64 rd_0 = R_rd_0.read(ba);
5597  rd += rd_0;
5598  etiss_uint64 rs3 = 0;
5599  static BitArrayRange R_rs3_0 (31,27);
5600  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5601  rs3 += rs3_0;
5602  etiss_uint64 rm = 0;
5603  static BitArrayRange R_rm_0 (14,12);
5604  etiss_uint64 rm_0 = R_rm_0.read(ba);
5605  rm += rm_0;
5606  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5607  partInit.getAffectedRegisters().add(reg_name[rd],64);
5608  partInit.getAffectedRegisters().add("instructionPointer",64);
5609  partInit.code() = std::string("//fnmsub.s\n")+
5610  "etiss_uint32 temp = 0;\n"
5611  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5612  #if RISCV64_Pipeline1
5613  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5614  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5615  "etiss_uint32 num_stages = 4;\n"
5616  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5617  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5618  #endif
5619  #if RISCV64_Pipeline2
5620  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5621  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5622  "etiss_uint32 num_stages = 4;\n"
5623  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5624  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5625  #endif
5626 
5627  "etiss_uint32 res = 0;\n"
5628  "etiss_int64 upper = 0;\n"
5629  "etiss_uint32 flags = 0;\n"
5630  "etiss_uint32 frs1 = 0;\n"
5631  "etiss_uint32 choose1 = 0;\n"
5632  "etiss_uint32 frs2 = 0;\n"
5633  "etiss_uint32 frs3 = 0;\n"
5634 
5635 "if(64 == 32)\n"
5636 "{\n"
5637  "if(" + toString(rm) + " < 7)\n"
5638  "{\n"
5639  "choose1 = (" + toString(rm) + " & 0xff);\n"
5640  #if RISCV64_DEBUG_CALL
5641  "printf(\"choose1 = %#x\\n\",choose1); \n"
5642  #endif
5643  "}\n"
5644 
5645  "else\n"
5646  "{\n"
5647  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5648  #if RISCV64_DEBUG_CALL
5649  "printf(\"choose1 = %#x\\n\",choose1); \n"
5650  #endif
5651  "}\n"
5652  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], ((RISCV64*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)3, choose1);\n"
5653  #if RISCV64_DEBUG_CALL
5654  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5655  #endif
5656 "}\n"
5657 
5658 "else\n"
5659 "{\n"
5660  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
5661  #if RISCV64_DEBUG_CALL
5662  "printf(\"frs1 = %#x\\n\",frs1); \n"
5663  #endif
5664  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
5665  #if RISCV64_DEBUG_CALL
5666  "printf(\"frs2 = %#x\\n\",frs2); \n"
5667  #endif
5668  "frs3 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs3) + "]);\n"
5669  #if RISCV64_DEBUG_CALL
5670  "printf(\"frs3 = %#x\\n\",frs3); \n"
5671  #endif
5672  "if(" + toString(rm) + " < 7)\n"
5673  "{\n"
5674  "choose1 = (" + toString(rm) + " & 0xff);\n"
5675  #if RISCV64_DEBUG_CALL
5676  "printf(\"choose1 = %#x\\n\",choose1); \n"
5677  #endif
5678  "}\n"
5679 
5680  "else\n"
5681  "{\n"
5682  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5683  #if RISCV64_DEBUG_CALL
5684  "printf(\"choose1 = %#x\\n\",choose1); \n"
5685  #endif
5686  "}\n"
5687  "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)3, choose1);\n"
5688  #if RISCV64_DEBUG_CALL
5689  "printf(\"res = %#x\\n\",res); \n"
5690  #endif
5691  "upper = - 1;\n"
5692  #if RISCV64_DEBUG_CALL
5693  "printf(\"upper = %#lx\\n\",upper); \n"
5694  #endif
5695  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
5696  #if RISCV64_DEBUG_CALL
5697  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5698  #endif
5699 "}\n"
5700 "flags = fget_flags();\n"
5701 #if RISCV64_DEBUG_CALL
5702 "printf(\"flags = %#x\\n\",flags); \n"
5703 #endif
5704 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5705 #if RISCV64_DEBUG_CALL
5706 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5707 #endif
5708 
5709  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5710 
5711 ;
5712 return true;
5713 },
5714 0,
5715 nullptr
5716 );
5717 //-------------------------------------------------------------------------------------------------------------------
5718 static InstructionDefinition fmadd_d_rd_frs1_frs2_frs3(
5719  ISA32_RISCV64,
5720  "fmadd.d",
5721  (uint32_t)0x2000043,
5722  (uint32_t) 0x600007f,
5723  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5724  {
5725  etiss_uint64 rs2 = 0;
5726  static BitArrayRange R_rs2_0 (24,20);
5727  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5728  rs2 += rs2_0;
5729  etiss_uint64 rs1 = 0;
5730  static BitArrayRange R_rs1_0 (19,15);
5731  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5732  rs1 += rs1_0;
5733  etiss_uint64 rd = 0;
5734  static BitArrayRange R_rd_0 (11,7);
5735  etiss_uint64 rd_0 = R_rd_0.read(ba);
5736  rd += rd_0;
5737  etiss_uint64 rs3 = 0;
5738  static BitArrayRange R_rs3_0 (31,27);
5739  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5740  rs3 += rs3_0;
5741  etiss_uint64 rm = 0;
5742  static BitArrayRange R_rm_0 (14,12);
5743  etiss_uint64 rm_0 = R_rm_0.read(ba);
5744  rm += rm_0;
5745  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5746  partInit.getAffectedRegisters().add(reg_name[rd],64);
5747  partInit.getAffectedRegisters().add("instructionPointer",64);
5748  partInit.code() = std::string("//fmadd.d\n")+
5749  "etiss_uint32 temp = 0;\n"
5750  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5751  #if RISCV64_Pipeline1
5752  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5753  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5754  "etiss_uint32 num_stages = 4;\n"
5755  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5756  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5757  #endif
5758  #if RISCV64_Pipeline2
5759  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5760  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5761  "etiss_uint32 num_stages = 4;\n"
5762  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5763  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5764  #endif
5765 
5766  "etiss_uint64 res = 0;\n"
5767  "etiss_int64 upper = 0;\n"
5768  "etiss_uint32 flags = 0;\n"
5769  "etiss_uint32 choose1 = 0;\n"
5770 
5771 "if(" + toString(rm) + " < 7)\n"
5772 "{\n"
5773  "choose1 = (" + toString(rm) + " & 0xff);\n"
5774  #if RISCV64_DEBUG_CALL
5775  "printf(\"choose1 = %#x\\n\",choose1); \n"
5776  #endif
5777 "}\n"
5778 
5779 "else\n"
5780 "{\n"
5781  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5782  #if RISCV64_DEBUG_CALL
5783  "printf(\"choose1 = %#x\\n\",choose1); \n"
5784  #endif
5785 "}\n"
5786 "res = fmadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint64)0, choose1);\n"
5787 #if RISCV64_DEBUG_CALL
5788 "printf(\"res = %#lx\\n\",res); \n"
5789 #endif
5790 "if(64 == 64)\n"
5791 "{\n"
5792  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
5793  #if RISCV64_DEBUG_CALL
5794  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5795  #endif
5796 "}\n"
5797 
5798 "else\n"
5799 "{\n"
5800  "upper = - 1;\n"
5801  #if RISCV64_DEBUG_CALL
5802  "printf(\"upper = %#lx\\n\",upper); \n"
5803  #endif
5804  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
5805  #if RISCV64_DEBUG_CALL
5806  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5807  #endif
5808 "}\n"
5809 "flags = fget_flags();\n"
5810 #if RISCV64_DEBUG_CALL
5811 "printf(\"flags = %#x\\n\",flags); \n"
5812 #endif
5813 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5814 #if RISCV64_DEBUG_CALL
5815 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5816 #endif
5817 
5818  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5819 
5820 ;
5821 return true;
5822 },
5823 0,
5824 nullptr
5825 );
5826 //-------------------------------------------------------------------------------------------------------------------
5827 static InstructionDefinition fmsub_d_rd_frs1_frs2_frs3(
5828  ISA32_RISCV64,
5829  "fmsub.d",
5830  (uint32_t)0x2000047,
5831  (uint32_t) 0x600007f,
5832  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5833  {
5834  etiss_uint64 rs2 = 0;
5835  static BitArrayRange R_rs2_0 (24,20);
5836  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5837  rs2 += rs2_0;
5838  etiss_uint64 rs1 = 0;
5839  static BitArrayRange R_rs1_0 (19,15);
5840  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5841  rs1 += rs1_0;
5842  etiss_uint64 rd = 0;
5843  static BitArrayRange R_rd_0 (11,7);
5844  etiss_uint64 rd_0 = R_rd_0.read(ba);
5845  rd += rd_0;
5846  etiss_uint64 rs3 = 0;
5847  static BitArrayRange R_rs3_0 (31,27);
5848  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5849  rs3 += rs3_0;
5850  etiss_uint64 rm = 0;
5851  static BitArrayRange R_rm_0 (14,12);
5852  etiss_uint64 rm_0 = R_rm_0.read(ba);
5853  rm += rm_0;
5854  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5855  partInit.getAffectedRegisters().add(reg_name[rd],64);
5856  partInit.getAffectedRegisters().add("instructionPointer",64);
5857  partInit.code() = std::string("//fmsub.d\n")+
5858  "etiss_uint32 temp = 0;\n"
5859  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5860  #if RISCV64_Pipeline1
5861  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5862  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5863  "etiss_uint32 num_stages = 4;\n"
5864  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5865  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5866  #endif
5867  #if RISCV64_Pipeline2
5868  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5869  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5870  "etiss_uint32 num_stages = 4;\n"
5871  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5872  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5873  #endif
5874 
5875  "etiss_uint64 res = 0;\n"
5876  "etiss_int64 upper = 0;\n"
5877  "etiss_uint32 flags = 0;\n"
5878  "etiss_uint32 choose1 = 0;\n"
5879 
5880 "if(" + toString(rm) + " < 7)\n"
5881 "{\n"
5882  "choose1 = (" + toString(rm) + " & 0xff);\n"
5883  #if RISCV64_DEBUG_CALL
5884  "printf(\"choose1 = %#x\\n\",choose1); \n"
5885  #endif
5886 "}\n"
5887 
5888 "else\n"
5889 "{\n"
5890  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5891  #if RISCV64_DEBUG_CALL
5892  "printf(\"choose1 = %#x\\n\",choose1); \n"
5893  #endif
5894 "}\n"
5895 "res = fmadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint32)1, choose1);\n"
5896 #if RISCV64_DEBUG_CALL
5897 "printf(\"res = %#lx\\n\",res); \n"
5898 #endif
5899 "if(64 == 64)\n"
5900 "{\n"
5901  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
5902  #if RISCV64_DEBUG_CALL
5903  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5904  #endif
5905 "}\n"
5906 
5907 "else\n"
5908 "{\n"
5909  "upper = - 1;\n"
5910  #if RISCV64_DEBUG_CALL
5911  "printf(\"upper = %#lx\\n\",upper); \n"
5912  #endif
5913  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
5914  #if RISCV64_DEBUG_CALL
5915  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5916  #endif
5917 "}\n"
5918 "flags = fget_flags();\n"
5919 #if RISCV64_DEBUG_CALL
5920 "printf(\"flags = %#x\\n\",flags); \n"
5921 #endif
5922 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5923 #if RISCV64_DEBUG_CALL
5924 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5925 #endif
5926 
5927  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5928 
5929 ;
5930 return true;
5931 },
5932 0,
5933 nullptr
5934 );
5935 //-------------------------------------------------------------------------------------------------------------------
5936 static InstructionDefinition fnmadd_d_rd_frs1_frs2_frs3(
5937  ISA32_RISCV64,
5938  "fnmadd.d",
5939  (uint32_t)0x200004f,
5940  (uint32_t) 0x600007f,
5941  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5942  {
5943  etiss_uint64 rs2 = 0;
5944  static BitArrayRange R_rs2_0 (24,20);
5945  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5946  rs2 += rs2_0;
5947  etiss_uint64 rs1 = 0;
5948  static BitArrayRange R_rs1_0 (19,15);
5949  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5950  rs1 += rs1_0;
5951  etiss_uint64 rd = 0;
5952  static BitArrayRange R_rd_0 (11,7);
5953  etiss_uint64 rd_0 = R_rd_0.read(ba);
5954  rd += rd_0;
5955  etiss_uint64 rs3 = 0;
5956  static BitArrayRange R_rs3_0 (31,27);
5957  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5958  rs3 += rs3_0;
5959  etiss_uint64 rm = 0;
5960  static BitArrayRange R_rm_0 (14,12);
5961  etiss_uint64 rm_0 = R_rm_0.read(ba);
5962  rm += rm_0;
5963  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5964  partInit.getAffectedRegisters().add(reg_name[rd],64);
5965  partInit.getAffectedRegisters().add("instructionPointer",64);
5966  partInit.code() = std::string("//fnmadd.d\n")+
5967  "etiss_uint32 temp = 0;\n"
5968  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5969  #if RISCV64_Pipeline1
5970  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5971  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5972  "etiss_uint32 num_stages = 4;\n"
5973  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5974  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5975  #endif
5976  #if RISCV64_Pipeline2
5977  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5978  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5979  "etiss_uint32 num_stages = 4;\n"
5980  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5981  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5982  #endif
5983 
5984  "etiss_uint64 res = 0;\n"
5985  "etiss_int64 upper = 0;\n"
5986  "etiss_uint32 flags = 0;\n"
5987  "etiss_uint32 choose1 = 0;\n"
5988 
5989 "if(" + toString(rm) + " < 7)\n"
5990 "{\n"
5991  "choose1 = (" + toString(rm) + " & 0xff);\n"
5992  #if RISCV64_DEBUG_CALL
5993  "printf(\"choose1 = %#x\\n\",choose1); \n"
5994  #endif
5995 "}\n"
5996 
5997 "else\n"
5998 "{\n"
5999  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
6000  #if RISCV64_DEBUG_CALL
6001  "printf(\"choose1 = %#x\\n\",choose1); \n"
6002  #endif
6003 "}\n"
6004 "res = fmadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint32)2, choose1);\n"
6005 #if RISCV64_DEBUG_CALL
6006 "printf(\"res = %#lx\\n\",res); \n"
6007 #endif
6008 "if(64 == 64)\n"
6009 "{\n"
6010  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
6011  #if RISCV64_DEBUG_CALL
6012  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
6013  #endif
6014 "}\n"
6015 
6016 "else\n"
6017 "{\n"
6018  "upper = - 1;\n"
6019  #if RISCV64_DEBUG_CALL
6020  "printf(\"upper = %#lx\\n\",upper); \n"
6021  #endif
6022  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
6023  #if RISCV64_DEBUG_CALL
6024  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
6025  #endif
6026 "}\n"
6027 "flags = fget_flags();\n"
6028 #if RISCV64_DEBUG_CALL
6029 "printf(\"flags = %#x\\n\",flags); \n"
6030 #endif
6031 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
6032 #if RISCV64_DEBUG_CALL
6033 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
6034 #endif
6035 
6036  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6037 
6038 ;
6039 return true;
6040 },
6041 0,
6042 nullptr
6043 );
6044 //-------------------------------------------------------------------------------------------------------------------
6045 static InstructionDefinition fnmsub_d_rd_frs1_frs2_frs3(
6046  ISA32_RISCV64,
6047  "fnmsub.d",
6048  (uint32_t)0x200004b,
6049  (uint32_t) 0x600007f,
6050  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6051  {
6052  etiss_uint64 rs2 = 0;
6053  static BitArrayRange R_rs2_0 (24,20);
6054  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6055  rs2 += rs2_0;
6056  etiss_uint64 rs1 = 0;
6057  static BitArrayRange R_rs1_0 (19,15);
6058  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6059  rs1 += rs1_0;
6060  etiss_uint64 rd = 0;
6061  static BitArrayRange R_rd_0 (11,7);
6062  etiss_uint64 rd_0 = R_rd_0.read(ba);
6063  rd += rd_0;
6064  etiss_uint64 rs3 = 0;
6065  static BitArrayRange R_rs3_0 (31,27);
6066  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
6067  rs3 += rs3_0;
6068  etiss_uint64 rm = 0;
6069  static BitArrayRange R_rm_0 (14,12);
6070  etiss_uint64 rm_0 = R_rm_0.read(ba);
6071  rm += rm_0;
6072  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6073  partInit.getAffectedRegisters().add(reg_name[rd],64);
6074  partInit.getAffectedRegisters().add("instructionPointer",64);
6075  partInit.code() = std::string("//fnmsub.d\n")+
6076  "etiss_uint32 temp = 0;\n"
6077  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6078  #if RISCV64_Pipeline1
6079  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6080  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6081  "etiss_uint32 num_stages = 4;\n"
6082  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6083  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6084  #endif
6085  #if RISCV64_Pipeline2
6086  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6087  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6088  "etiss_uint32 num_stages = 4;\n"
6089  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6090  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6091  #endif
6092 
6093  "etiss_uint64 res = 0;\n"
6094  "etiss_int64 upper = 0;\n"
6095  "etiss_uint32 flags = 0;\n"
6096  "etiss_uint32 choose1 = 0;\n"
6097 
6098 "if(" + toString(rm) + " < 7)\n"
6099 "{\n"
6100  "choose1 = (" + toString(rm) + " & 0xff);\n"
6101  #if RISCV64_DEBUG_CALL
6102  "printf(\"choose1 = %#x\\n\",choose1); \n"
6103  #endif
6104 "}\n"
6105 
6106 "else\n"
6107 "{\n"
6108  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
6109  #if RISCV64_DEBUG_CALL
6110  "printf(\"choose1 = %#x\\n\",choose1); \n"
6111  #endif
6112 "}\n"
6113 "res = fmadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint32)3, choose1);\n"
6114 #if RISCV64_DEBUG_CALL
6115 "printf(\"res = %#lx\\n\",res); \n"
6116 #endif
6117 "if(64 == 64)\n"
6118 "{\n"
6119  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
6120  #if RISCV64_DEBUG_CALL
6121  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
6122  #endif
6123 "}\n"
6124 
6125 "else\n"
6126 "{\n"
6127  "upper = - 1;\n"
6128  #if RISCV64_DEBUG_CALL
6129  "printf(\"upper = %#lx\\n\",upper); \n"
6130  #endif
6131  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
6132  #if RISCV64_DEBUG_CALL
6133  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
6134  #endif
6135 "}\n"
6136 "flags = fget_flags();\n"
6137 #if RISCV64_DEBUG_CALL
6138 "printf(\"flags = %#x\\n\",flags); \n"
6139 #endif
6140 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
6141 #if RISCV64_DEBUG_CALL
6142 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
6143 #endif
6144 
6145  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6146 
6147 ;
6148 return true;
6149 },
6150 0,
6151 nullptr
6152 );
6153 //-------------------------------------------------------------------------------------------------------------------
6154 static InstructionDefinition slli_rd_rs1_shamt(
6155  ISA32_RISCV64,
6156  "slli",
6157  (uint32_t)0x1013,
6158  (uint32_t) 0xfc00707f,
6159  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6160  {
6161  etiss_uint64 rs1 = 0;
6162  static BitArrayRange R_rs1_0 (19,15);
6163  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6164  rs1 += rs1_0;
6165  etiss_uint64 rd = 0;
6166  static BitArrayRange R_rd_0 (11,7);
6167  etiss_uint64 rd_0 = R_rd_0.read(ba);
6168  rd += rd_0;
6169  etiss_uint64 shamt = 0;
6170  static BitArrayRange R_shamt_0 (25,20);
6171  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6172  shamt += shamt_0;
6173  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6174  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6175  partInit.getAffectedRegisters().add(reg_name[rd],64);
6176  partInit.getAffectedRegisters().add("instructionPointer",64);
6177  partInit.code() = std::string("//slli\n")+
6178  "etiss_uint32 temp = 0;\n"
6179  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6180  #if RISCV64_Pipeline1
6181  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6182  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6183  "etiss_uint32 num_stages = 4;\n"
6184  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6185  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6186  #endif
6187  #if RISCV64_Pipeline2
6188  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6189  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6190  "etiss_uint32 num_stages = 4;\n"
6191  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6192  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6193  #endif
6194 
6195 
6196 "if(" + toString(rd) + " != 0)\n"
6197 "{\n"
6198  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] << " + toString(shamt) + ");\n"
6199  #if RISCV64_DEBUG_CALL
6200  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6201  #endif
6202 "}\n"
6203 
6204 
6205  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6206 
6207 ;
6208 return true;
6209 },
6210 0,
6211 nullptr
6212 );
6213 //-------------------------------------------------------------------------------------------------------------------
6214 static InstructionDefinition srli_rd_rs1_shamt(
6215  ISA32_RISCV64,
6216  "srli",
6217  (uint32_t)0x5013,
6218  (uint32_t) 0xfc00707f,
6219  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6220  {
6221  etiss_uint64 rs1 = 0;
6222  static BitArrayRange R_rs1_0 (19,15);
6223  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6224  rs1 += rs1_0;
6225  etiss_uint64 rd = 0;
6226  static BitArrayRange R_rd_0 (11,7);
6227  etiss_uint64 rd_0 = R_rd_0.read(ba);
6228  rd += rd_0;
6229  etiss_uint64 shamt = 0;
6230  static BitArrayRange R_shamt_0 (25,20);
6231  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6232  shamt += shamt_0;
6233  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6234  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6235  partInit.getAffectedRegisters().add(reg_name[rd],64);
6236  partInit.getAffectedRegisters().add("instructionPointer",64);
6237  partInit.code() = std::string("//srli\n")+
6238  "etiss_uint32 temp = 0;\n"
6239  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6240  #if RISCV64_Pipeline1
6241  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6242  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6243  "etiss_uint32 num_stages = 4;\n"
6244  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6245  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6246  #endif
6247  #if RISCV64_Pipeline2
6248  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6249  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6250  "etiss_uint32 num_stages = 4;\n"
6251  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6252  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6253  #endif
6254 
6255 
6256 "if(" + toString(rd) + " != 0)\n"
6257 "{\n"
6258  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] >> " + toString(shamt) + ");\n"
6259  #if RISCV64_DEBUG_CALL
6260  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6261  #endif
6262 "}\n"
6263 
6264 
6265  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6266 
6267 ;
6268 return true;
6269 },
6270 0,
6271 nullptr
6272 );
6273 //-------------------------------------------------------------------------------------------------------------------
6274 static InstructionDefinition srai_rd_rs1_shamt(
6275  ISA32_RISCV64,
6276  "srai",
6277  (uint32_t)0x40005013,
6278  (uint32_t) 0xfc00707f,
6279  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6280  {
6281  etiss_uint64 rs1 = 0;
6282  static BitArrayRange R_rs1_0 (19,15);
6283  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6284  rs1 += rs1_0;
6285  etiss_uint64 rd = 0;
6286  static BitArrayRange R_rd_0 (11,7);
6287  etiss_uint64 rd_0 = R_rd_0.read(ba);
6288  rd += rd_0;
6289  etiss_uint64 shamt = 0;
6290  static BitArrayRange R_shamt_0 (25,20);
6291  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6292  shamt += shamt_0;
6293  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6294  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6295  partInit.getAffectedRegisters().add(reg_name[rd],64);
6296  partInit.getAffectedRegisters().add("instructionPointer",64);
6297  partInit.code() = std::string("//srai\n")+
6298  "etiss_uint32 temp = 0;\n"
6299  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6300  #if RISCV64_Pipeline1
6301  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6302  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6303  "etiss_uint32 num_stages = 4;\n"
6304  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6305  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6306  #endif
6307  #if RISCV64_Pipeline2
6308  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6309  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6310  "etiss_uint32 num_stages = 4;\n"
6311  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6312  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6313  #endif
6314 
6315 
6316 "if(" + toString(rd) + " != 0)\n"
6317 "{\n"
6318  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
6319  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
6320  "{\n"
6321  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
6322  "}\n"
6323  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 >> " + toString(shamt) + ");\n"
6324  #if RISCV64_DEBUG_CALL
6325  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6326  #endif
6327 "}\n"
6328 
6329 
6330  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6331 
6332 ;
6333 return true;
6334 },
6335 0,
6336 nullptr
6337 );
6338 //-------------------------------------------------------------------------------------------------------------------
6339 static InstructionDefinition add_rd_rs1_rs2(
6340  ISA32_RISCV64,
6341  "add",
6342  (uint32_t)0x33,
6343  (uint32_t) 0xfe00707f,
6344  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6345  {
6346  etiss_uint64 rs2 = 0;
6347  static BitArrayRange R_rs2_0 (24,20);
6348  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6349  rs2 += rs2_0;
6350  etiss_uint64 rs1 = 0;
6351  static BitArrayRange R_rs1_0 (19,15);
6352  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6353  rs1 += rs1_0;
6354  etiss_uint64 rd = 0;
6355  static BitArrayRange R_rd_0 (11,7);
6356  etiss_uint64 rd_0 = R_rd_0.read(ba);
6357  rd += rd_0;
6358  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6359  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6360  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6361  partInit.getAffectedRegisters().add(reg_name[rd],64);
6362  partInit.getAffectedRegisters().add("instructionPointer",64);
6363  partInit.code() = std::string("//add\n")+
6364  "etiss_uint32 temp = 0;\n"
6365  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6366  #if RISCV64_Pipeline1
6367  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6368  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6369  "etiss_uint32 num_stages = 4;\n"
6370  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6371  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6372  #endif
6373  #if RISCV64_Pipeline2
6374  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6375  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6376  "etiss_uint32 num_stages = 4;\n"
6377  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6378  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6379  #endif
6380 
6381 
6382 "if(" + toString(rd) + " != 0)\n"
6383 "{\n"
6384  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs1) + "] + *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
6385  #if RISCV64_DEBUG_CALL
6386  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6387  #endif
6388 "}\n"
6389 
6390 
6391  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6392 
6393 ;
6394 return true;
6395 },
6396 0,
6397 nullptr
6398 );
6399 //-------------------------------------------------------------------------------------------------------------------
6400 static InstructionDefinition addw_(
6401  ISA32_RISCV64,
6402  "addw",
6403  (uint32_t)0x3b,
6404  (uint32_t) 0xfe00707f,
6405  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6406  {
6407  etiss_uint64 rs2 = 0;
6408  static BitArrayRange R_rs2_0 (24,20);
6409  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6410  rs2 += rs2_0;
6411  etiss_uint64 rs1 = 0;
6412  static BitArrayRange R_rs1_0 (19,15);
6413  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6414  rs1 += rs1_0;
6415  etiss_uint64 rd = 0;
6416  static BitArrayRange R_rd_0 (11,7);
6417  etiss_uint64 rd_0 = R_rd_0.read(ba);
6418  rd += rd_0;
6419  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6420  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6421  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6422  partInit.getAffectedRegisters().add(reg_name[rd],64);
6423  partInit.getAffectedRegisters().add("instructionPointer",64);
6424  partInit.code() = std::string("//addw\n")+
6425  "etiss_uint32 temp = 0;\n"
6426  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6427  #if RISCV64_Pipeline1
6428  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6429  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6430  "etiss_uint32 num_stages = 4;\n"
6431  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6432  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6433  #endif
6434  #if RISCV64_Pipeline2
6435  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6436  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6437  "etiss_uint32 num_stages = 4;\n"
6438  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6439  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6440  #endif
6441 
6442  "etiss_uint32 res = 0;\n"
6443 
6444 "if(" + toString(rd) + " != 0)\n"
6445 "{\n"
6446  "res = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) + (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff);\n"
6447  #if RISCV64_DEBUG_CALL
6448  "printf(\"res = %#x\\n\",res); \n"
6449  #endif
6450  "etiss_int32 cast_0 = res; \n"
6451  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
6452  "{\n"
6453  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
6454  "}\n"
6455  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
6456  #if RISCV64_DEBUG_CALL
6457  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6458  #endif
6459 "}\n"
6460 
6461 
6462  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6463 
6464 ;
6465 return true;
6466 },
6467 0,
6468 nullptr
6469 );
6470 //-------------------------------------------------------------------------------------------------------------------
6471 static InstructionDefinition sll_rd_rs1_rs2(
6472  ISA32_RISCV64,
6473  "sll",
6474  (uint32_t)0x1033,
6475  (uint32_t) 0xfe00707f,
6476  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6477  {
6478  etiss_uint64 rs2 = 0;
6479  static BitArrayRange R_rs2_0 (24,20);
6480  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6481  rs2 += rs2_0;
6482  etiss_uint64 rs1 = 0;
6483  static BitArrayRange R_rs1_0 (19,15);
6484  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6485  rs1 += rs1_0;
6486  etiss_uint64 rd = 0;
6487  static BitArrayRange R_rd_0 (11,7);
6488  etiss_uint64 rd_0 = R_rd_0.read(ba);
6489  rd += rd_0;
6490  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6491  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6492  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6493  partInit.getAffectedRegisters().add(reg_name[rd],64);
6494  partInit.getAffectedRegisters().add("instructionPointer",64);
6495  partInit.code() = std::string("//sll\n")+
6496  "etiss_uint32 temp = 0;\n"
6497  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6498  #if RISCV64_Pipeline1
6499  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6500  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {4, 5}, {6, 7}};\n"
6501  "etiss_uint32 num_stages = 4;\n"
6502  "etiss_uint32 num_resources[100] = {2, 1, 2, 2};\n"
6503  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6504  #endif
6505  #if RISCV64_Pipeline2
6506  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6507  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {4, 5}, {6, 7}};\n"
6508  "etiss_uint32 num_stages = 4;\n"
6509  "etiss_uint32 num_resources[100] = {2, 1, 2, 2};\n"
6510  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6511  #endif
6512 
6513 
6514 "if(" + toString(rd) + " != 0)\n"
6515 "{\n"
6516  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] << (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 64 - 1));\n"
6517  #if RISCV64_DEBUG_CALL
6518  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6519  #endif
6520 "}\n"
6521 
6522 
6523  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6524 
6525 ;
6526 return true;
6527 },
6528 0,
6529 nullptr
6530 );
6531 //-------------------------------------------------------------------------------------------------------------------
6532 static InstructionDefinition slliw_rd_rs1_shamt(
6533  ISA32_RISCV64,
6534  "slliw",
6535  (uint32_t)0x101b,
6536  (uint32_t) 0xfe00707f,
6537  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6538  {
6539  etiss_uint64 rs1 = 0;
6540  static BitArrayRange R_rs1_0 (19,15);
6541  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6542  rs1 += rs1_0;
6543  etiss_uint64 rd = 0;
6544  static BitArrayRange R_rd_0 (11,7);
6545  etiss_uint64 rd_0 = R_rd_0.read(ba);
6546  rd += rd_0;
6547  etiss_uint64 shamt = 0;
6548  static BitArrayRange R_shamt_0 (24,20);
6549  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6550  shamt += shamt_0;
6551  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6552  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6553  partInit.getAffectedRegisters().add(reg_name[rd],64);
6554  partInit.getAffectedRegisters().add("instructionPointer",64);
6555  partInit.code() = std::string("//slliw\n")+
6556  "etiss_uint32 temp = 0;\n"
6557  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6558  #if RISCV64_Pipeline1
6559  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6560  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6561  "etiss_uint32 num_stages = 4;\n"
6562  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6563  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6564  #endif
6565  #if RISCV64_Pipeline2
6566  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6567  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6568  "etiss_uint32 num_stages = 4;\n"
6569  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6570  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6571  #endif
6572 
6573  "etiss_uint32 sh_val = 0;\n"
6574 
6575 "if(" + toString(rd) + " != 0)\n"
6576 "{\n"
6577  "sh_val = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) << " + toString(shamt) + ");\n"
6578  #if RISCV64_DEBUG_CALL
6579  "printf(\"sh_val = %#x\\n\",sh_val); \n"
6580  #endif
6581  "etiss_int32 cast_0 = sh_val; \n"
6582  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
6583  "{\n"
6584  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
6585  "}\n"
6586  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
6587  #if RISCV64_DEBUG_CALL
6588  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6589  #endif
6590 "}\n"
6591 
6592 
6593  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6594 
6595 ;
6596 return true;
6597 },
6598 0,
6599 nullptr
6600 );
6601 //-------------------------------------------------------------------------------------------------------------------
6602 static InstructionDefinition sllw_rd_rs1_rs2(
6603  ISA32_RISCV64,
6604  "sllw",
6605  (uint32_t)0x103b,
6606  (uint32_t) 0xfe00707f,
6607  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6608  {
6609  etiss_uint64 rs2 = 0;
6610  static BitArrayRange R_rs2_0 (24,20);
6611  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6612  rs2 += rs2_0;
6613  etiss_uint64 rs1 = 0;
6614  static BitArrayRange R_rs1_0 (19,15);
6615  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6616  rs1 += rs1_0;
6617  etiss_uint64 rd = 0;
6618  static BitArrayRange R_rd_0 (11,7);
6619  etiss_uint64 rd_0 = R_rd_0.read(ba);
6620  rd += rd_0;
6621  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6622  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6623  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6624  partInit.getAffectedRegisters().add(reg_name[rd],64);
6625  partInit.getAffectedRegisters().add("instructionPointer",64);
6626  partInit.code() = std::string("//sllw\n")+
6627  "etiss_uint32 temp = 0;\n"
6628  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6629  #if RISCV64_Pipeline1
6630  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6631  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6632  "etiss_uint32 num_stages = 4;\n"
6633  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6634  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6635  #endif
6636  #if RISCV64_Pipeline2
6637  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6638  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6639  "etiss_uint32 num_stages = 4;\n"
6640  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6641  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6642  #endif
6643 
6644  "etiss_uint32 sh_val = 0;\n"
6645  "etiss_uint32 count = 0;\n"
6646  "etiss_int32 mask = 0;\n"
6647 
6648 "if(" + toString(rd) + " != 0)\n"
6649 "{\n"
6650  "mask = 31;\n"
6651  #if RISCV64_DEBUG_CALL
6652  "printf(\"mask = %#x\\n\",mask); \n"
6653  #endif
6654  "count = ((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) & mask);\n"
6655  #if RISCV64_DEBUG_CALL
6656  "printf(\"count = %#x\\n\",count); \n"
6657  #endif
6658  "sh_val = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) << count);\n"
6659  #if RISCV64_DEBUG_CALL
6660  "printf(\"sh_val = %#x\\n\",sh_val); \n"
6661  #endif
6662  "etiss_int32 cast_0 = sh_val; \n"
6663  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
6664  "{\n"
6665  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
6666  "}\n"
6667  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
6668  #if RISCV64_DEBUG_CALL
6669  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6670  #endif
6671 "}\n"
6672 
6673 
6674  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6675 
6676 ;
6677 return true;
6678 },
6679 0,
6680 nullptr
6681 );
6682 //-------------------------------------------------------------------------------------------------------------------
6683 static InstructionDefinition slt_rd_rs1_rs2(
6684  ISA32_RISCV64,
6685  "slt",
6686  (uint32_t)0x2033,
6687  (uint32_t) 0xfe00707f,
6688  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6689  {
6690  etiss_uint64 rs2 = 0;
6691  static BitArrayRange R_rs2_0 (24,20);
6692  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6693  rs2 += rs2_0;
6694  etiss_uint64 rs1 = 0;
6695  static BitArrayRange R_rs1_0 (19,15);
6696  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6697  rs1 += rs1_0;
6698  etiss_uint64 rd = 0;
6699  static BitArrayRange R_rd_0 (11,7);
6700  etiss_uint64 rd_0 = R_rd_0.read(ba);
6701  rd += rd_0;
6702  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6703  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6704  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6705  partInit.getAffectedRegisters().add(reg_name[rd],64);
6706  partInit.getAffectedRegisters().add("instructionPointer",64);
6707  partInit.code() = std::string("//slt\n")+
6708  "etiss_uint32 temp = 0;\n"
6709  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6710  #if RISCV64_Pipeline1
6711  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6712  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6713  "etiss_uint32 num_stages = 4;\n"
6714  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6715  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6716  #endif
6717  #if RISCV64_Pipeline2
6718  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6719  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6720  "etiss_uint32 num_stages = 4;\n"
6721  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6722  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6723  #endif
6724 
6725  "etiss_int8 choose1 = 0;\n"
6726 
6727 "if(" + toString(rd) + " != 0)\n"
6728 "{\n"
6729  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
6730  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
6731  "{\n"
6732  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
6733  "}\n"
6734  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
6735  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
6736  "{\n"
6737  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
6738  "}\n"
6739  "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n"
6740  "{\n"
6741  "choose1 = 1;\n"
6742  #if RISCV64_DEBUG_CALL
6743  "printf(\"choose1 = %#x\\n\",choose1); \n"
6744  #endif
6745  "}\n"
6746 
6747  "else\n"
6748  "{\n"
6749  "choose1 = 0;\n"
6750  #if RISCV64_DEBUG_CALL
6751  "printf(\"choose1 = %#x\\n\",choose1); \n"
6752  #endif
6753  "}\n"
6754  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = choose1;\n"
6755  #if RISCV64_DEBUG_CALL
6756  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6757  #endif
6758 "}\n"
6759 
6760 
6761  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6762 
6763 ;
6764 return true;
6765 },
6766 0,
6767 nullptr
6768 );
6769 //-------------------------------------------------------------------------------------------------------------------
6770 static InstructionDefinition sltu_rd_rs1_rs2(
6771  ISA32_RISCV64,
6772  "sltu",
6773  (uint32_t)0x3033,
6774  (uint32_t) 0xfe00707f,
6775  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6776  {
6777  etiss_uint64 rs2 = 0;
6778  static BitArrayRange R_rs2_0 (24,20);
6779  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6780  rs2 += rs2_0;
6781  etiss_uint64 rs1 = 0;
6782  static BitArrayRange R_rs1_0 (19,15);
6783  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6784  rs1 += rs1_0;
6785  etiss_uint64 rd = 0;
6786  static BitArrayRange R_rd_0 (11,7);
6787  etiss_uint64 rd_0 = R_rd_0.read(ba);
6788  rd += rd_0;
6789  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6790  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6791  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6792  partInit.getAffectedRegisters().add(reg_name[rd],64);
6793  partInit.getAffectedRegisters().add("instructionPointer",64);
6794  partInit.code() = std::string("//sltu\n")+
6795  "etiss_uint32 temp = 0;\n"
6796  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6797  #if RISCV64_Pipeline1
6798  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6799  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6800  "etiss_uint32 num_stages = 4;\n"
6801  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6802  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6803  #endif
6804  #if RISCV64_Pipeline2
6805  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6806  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6807  "etiss_uint32 num_stages = 4;\n"
6808  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6809  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6810  #endif
6811 
6812  "etiss_int8 choose1 = 0;\n"
6813 
6814 "if(" + toString(rd) + " != 0)\n"
6815 "{\n"
6816  "if((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "] < (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
6817  "{\n"
6818  "choose1 = 1;\n"
6819  #if RISCV64_DEBUG_CALL
6820  "printf(\"choose1 = %#x\\n\",choose1); \n"
6821  #endif
6822  "}\n"
6823 
6824  "else\n"
6825  "{\n"
6826  "choose1 = 0;\n"
6827  #if RISCV64_DEBUG_CALL
6828  "printf(\"choose1 = %#x\\n\",choose1); \n"
6829  #endif
6830  "}\n"
6831  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = choose1;\n"
6832  #if RISCV64_DEBUG_CALL
6833  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6834  #endif
6835 "}\n"
6836 
6837 
6838  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6839 
6840 ;
6841 return true;
6842 },
6843 0,
6844 nullptr
6845 );
6846 //-------------------------------------------------------------------------------------------------------------------
6847 static InstructionDefinition xor_rd_rs1_rs2(
6848  ISA32_RISCV64,
6849  "xor",
6850  (uint32_t)0x4033,
6851  (uint32_t) 0xfe00707f,
6852  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6853  {
6854  etiss_uint64 rs2 = 0;
6855  static BitArrayRange R_rs2_0 (24,20);
6856  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6857  rs2 += rs2_0;
6858  etiss_uint64 rs1 = 0;
6859  static BitArrayRange R_rs1_0 (19,15);
6860  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6861  rs1 += rs1_0;
6862  etiss_uint64 rd = 0;
6863  static BitArrayRange R_rd_0 (11,7);
6864  etiss_uint64 rd_0 = R_rd_0.read(ba);
6865  rd += rd_0;
6866  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6867  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6868  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6869  partInit.getAffectedRegisters().add(reg_name[rd],64);
6870  partInit.getAffectedRegisters().add("instructionPointer",64);
6871  partInit.code() = std::string("//xor\n")+
6872  "etiss_uint32 temp = 0;\n"
6873  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6874  #if RISCV64_Pipeline1
6875  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6876  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6877  "etiss_uint32 num_stages = 4;\n"
6878  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6879  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6880  #endif
6881  #if RISCV64_Pipeline2
6882  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6883  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6884  "etiss_uint32 num_stages = 4;\n"
6885  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6886  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6887  #endif
6888 
6889 
6890 "if(" + toString(rd) + " != 0)\n"
6891 "{\n"
6892  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] ^ *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
6893  #if RISCV64_DEBUG_CALL
6894  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6895  #endif
6896 "}\n"
6897 
6898 
6899  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6900 
6901 ;
6902 return true;
6903 },
6904 0,
6905 nullptr
6906 );
6907 //-------------------------------------------------------------------------------------------------------------------
6908 static InstructionDefinition srl_rd_rs1_rs2(
6909  ISA32_RISCV64,
6910  "srl",
6911  (uint32_t)0x5033,
6912  (uint32_t) 0xfe00707f,
6913  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6914  {
6915  etiss_uint64 rs2 = 0;
6916  static BitArrayRange R_rs2_0 (24,20);
6917  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6918  rs2 += rs2_0;
6919  etiss_uint64 rs1 = 0;
6920  static BitArrayRange R_rs1_0 (19,15);
6921  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6922  rs1 += rs1_0;
6923  etiss_uint64 rd = 0;
6924  static BitArrayRange R_rd_0 (11,7);
6925  etiss_uint64 rd_0 = R_rd_0.read(ba);
6926  rd += rd_0;
6927  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6928  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6929  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6930  partInit.getAffectedRegisters().add(reg_name[rd],64);
6931  partInit.getAffectedRegisters().add("instructionPointer",64);
6932  partInit.code() = std::string("//srl\n")+
6933  "etiss_uint32 temp = 0;\n"
6934  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6935  #if RISCV64_Pipeline1
6936  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6937  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6938  "etiss_uint32 num_stages = 4;\n"
6939  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6940  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6941  #endif
6942  #if RISCV64_Pipeline2
6943  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6944  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6945  "etiss_uint32 num_stages = 4;\n"
6946  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6947  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6948  #endif
6949 
6950 
6951 "if(" + toString(rd) + " != 0)\n"
6952 "{\n"
6953  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] >> (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 64 - 1));\n"
6954  #if RISCV64_DEBUG_CALL
6955  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6956  #endif
6957 "}\n"
6958 
6959 
6960  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6961 
6962 ;
6963 return true;
6964 },
6965 0,
6966 nullptr
6967 );
6968 //-------------------------------------------------------------------------------------------------------------------
6969 static InstructionDefinition srliw_rd_rs1_shamt(
6970  ISA32_RISCV64,
6971  "srliw",
6972  (uint32_t)0x501b,
6973  (uint32_t) 0xfe00707f,
6974  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6975  {
6976  etiss_uint64 rs1 = 0;
6977  static BitArrayRange R_rs1_0 (19,15);
6978  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6979  rs1 += rs1_0;
6980  etiss_uint64 rd = 0;
6981  static BitArrayRange R_rd_0 (11,7);
6982  etiss_uint64 rd_0 = R_rd_0.read(ba);
6983  rd += rd_0;
6984  etiss_uint64 shamt = 0;
6985  static BitArrayRange R_shamt_0 (24,20);
6986  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6987  shamt += shamt_0;
6988  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6989  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6990  partInit.getAffectedRegisters().add(reg_name[rd],64);
6991  partInit.getAffectedRegisters().add("instructionPointer",64);
6992  partInit.code() = std::string("//srliw\n")+
6993  "etiss_uint32 temp = 0;\n"
6994  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6995  #if RISCV64_Pipeline1
6996  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6997  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6998  "etiss_uint32 num_stages = 4;\n"
6999  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7000  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7001  #endif
7002  #if RISCV64_Pipeline2
7003  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7004  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7005  "etiss_uint32 num_stages = 4;\n"
7006  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7007  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7008  #endif
7009 
7010  "etiss_uint32 sh_val = 0;\n"
7011 
7012 "if(" + toString(rd) + " != 0)\n"
7013 "{\n"
7014  "sh_val = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) >> " + toString(shamt) + ");\n"
7015  #if RISCV64_DEBUG_CALL
7016  "printf(\"sh_val = %#x\\n\",sh_val); \n"
7017  #endif
7018  "etiss_int32 cast_0 = sh_val; \n"
7019  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
7020  "{\n"
7021  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
7022  "}\n"
7023  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
7024  #if RISCV64_DEBUG_CALL
7025  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7026  #endif
7027 "}\n"
7028 
7029 
7030  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7031 
7032 ;
7033 return true;
7034 },
7035 0,
7036 nullptr
7037 );
7038 //-------------------------------------------------------------------------------------------------------------------
7039 static InstructionDefinition srlw_rd_rs1_rs2(
7040  ISA32_RISCV64,
7041  "srlw",
7042  (uint32_t)0x503b,
7043  (uint32_t) 0xfe00707f,
7044  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7045  {
7046  etiss_uint64 rs2 = 0;
7047  static BitArrayRange R_rs2_0 (24,20);
7048  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7049  rs2 += rs2_0;
7050  etiss_uint64 rs1 = 0;
7051  static BitArrayRange R_rs1_0 (19,15);
7052  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7053  rs1 += rs1_0;
7054  etiss_uint64 rd = 0;
7055  static BitArrayRange R_rd_0 (11,7);
7056  etiss_uint64 rd_0 = R_rd_0.read(ba);
7057  rd += rd_0;
7058  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7059  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7060  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7061  partInit.getAffectedRegisters().add(reg_name[rd],64);
7062  partInit.getAffectedRegisters().add("instructionPointer",64);
7063  partInit.code() = std::string("//srlw\n")+
7064  "etiss_uint32 temp = 0;\n"
7065  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7066  #if RISCV64_Pipeline1
7067  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7068  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7069  "etiss_uint32 num_stages = 4;\n"
7070  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7071  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7072  #endif
7073  #if RISCV64_Pipeline2
7074  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7075  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7076  "etiss_uint32 num_stages = 4;\n"
7077  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7078  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7079  #endif
7080 
7081  "etiss_uint32 sh_val = 0;\n"
7082  "etiss_uint32 count = 0;\n"
7083  "etiss_int32 mask = 0;\n"
7084 
7085 "if(" + toString(rd) + " != 0)\n"
7086 "{\n"
7087  "mask = 31;\n"
7088  #if RISCV64_DEBUG_CALL
7089  "printf(\"mask = %#x\\n\",mask); \n"
7090  #endif
7091  "count = ((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) & mask);\n"
7092  #if RISCV64_DEBUG_CALL
7093  "printf(\"count = %#x\\n\",count); \n"
7094  #endif
7095  "sh_val = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) >> count);\n"
7096  #if RISCV64_DEBUG_CALL
7097  "printf(\"sh_val = %#x\\n\",sh_val); \n"
7098  #endif
7099  "etiss_int32 cast_0 = sh_val; \n"
7100  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
7101  "{\n"
7102  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
7103  "}\n"
7104  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
7105  #if RISCV64_DEBUG_CALL
7106  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7107  #endif
7108 "}\n"
7109 
7110 
7111  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7112 
7113 ;
7114 return true;
7115 },
7116 0,
7117 nullptr
7118 );
7119 //-------------------------------------------------------------------------------------------------------------------
7120 static InstructionDefinition or_rd_rs1_rs2(
7121  ISA32_RISCV64,
7122  "or",
7123  (uint32_t)0x6033,
7124  (uint32_t) 0xfe00707f,
7125  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7126  {
7127  etiss_uint64 rs2 = 0;
7128  static BitArrayRange R_rs2_0 (24,20);
7129  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7130  rs2 += rs2_0;
7131  etiss_uint64 rs1 = 0;
7132  static BitArrayRange R_rs1_0 (19,15);
7133  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7134  rs1 += rs1_0;
7135  etiss_uint64 rd = 0;
7136  static BitArrayRange R_rd_0 (11,7);
7137  etiss_uint64 rd_0 = R_rd_0.read(ba);
7138  rd += rd_0;
7139  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7140  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7141  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7142  partInit.getAffectedRegisters().add(reg_name[rd],64);
7143  partInit.getAffectedRegisters().add("instructionPointer",64);
7144  partInit.code() = std::string("//or\n")+
7145  "etiss_uint32 temp = 0;\n"
7146  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7147  #if RISCV64_Pipeline1
7148  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7149  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7150  "etiss_uint32 num_stages = 4;\n"
7151  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7152  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7153  #endif
7154  #if RISCV64_Pipeline2
7155  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7156  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7157  "etiss_uint32 num_stages = 4;\n"
7158  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7159  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7160  #endif
7161 
7162 
7163 "if(" + toString(rd) + " != 0)\n"
7164 "{\n"
7165  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] | *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
7166  #if RISCV64_DEBUG_CALL
7167  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7168  #endif
7169 "}\n"
7170 
7171 
7172  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7173 
7174 ;
7175 return true;
7176 },
7177 0,
7178 nullptr
7179 );
7180 //-------------------------------------------------------------------------------------------------------------------
7181 static InstructionDefinition and_rd_rs1_rs2(
7182  ISA32_RISCV64,
7183  "and",
7184  (uint32_t)0x7033,
7185  (uint32_t) 0xfe00707f,
7186  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7187  {
7188  etiss_uint64 rs2 = 0;
7189  static BitArrayRange R_rs2_0 (24,20);
7190  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7191  rs2 += rs2_0;
7192  etiss_uint64 rs1 = 0;
7193  static BitArrayRange R_rs1_0 (19,15);
7194  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7195  rs1 += rs1_0;
7196  etiss_uint64 rd = 0;
7197  static BitArrayRange R_rd_0 (11,7);
7198  etiss_uint64 rd_0 = R_rd_0.read(ba);
7199  rd += rd_0;
7200  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7201  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7202  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7203  partInit.getAffectedRegisters().add(reg_name[rd],64);
7204  partInit.getAffectedRegisters().add("instructionPointer",64);
7205  partInit.code() = std::string("//and\n")+
7206  "etiss_uint32 temp = 0;\n"
7207  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7208  #if RISCV64_Pipeline1
7209  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7210  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7211  "etiss_uint32 num_stages = 4;\n"
7212  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7213  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7214  #endif
7215  #if RISCV64_Pipeline2
7216  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7217  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7218  "etiss_uint32 num_stages = 4;\n"
7219  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7220  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7221  #endif
7222 
7223 
7224 "if(" + toString(rd) + " != 0)\n"
7225 "{\n"
7226  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
7227  #if RISCV64_DEBUG_CALL
7228  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7229  #endif
7230 "}\n"
7231 
7232 
7233  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7234 
7235 ;
7236 return true;
7237 },
7238 0,
7239 nullptr
7240 );
7241 //-------------------------------------------------------------------------------------------------------------------
7242 static InstructionDefinition uret_(
7243  ISA32_RISCV64,
7244  "uret",
7245  (uint32_t)0x200073,
7246  (uint32_t) 0xffffffff,
7247  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7248  {
7249  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7250  partInit.getAffectedRegisters().add("instructionPointer",64);
7251  partInit.code() = std::string("//uret\n")+
7252  "etiss_uint32 temp = 0;\n"
7253  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7254  #if RISCV64_Pipeline1
7255  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7256  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7257  "etiss_uint32 num_stages = 4;\n"
7258  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7259  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7260  #endif
7261  #if RISCV64_Pipeline2
7262  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7263  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7264  "etiss_uint32 num_stages = 4;\n"
7265  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7266  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7267  #endif
7268 
7269 
7270 "((RISCV64*)cpu)->CSR[3088] = 0;\n"//PRIVLV=0
7271 "((RISCV64*)cpu)->CSR[0] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[0] & 0x10)>>4)) ^ (((RISCV64*)cpu)->CSR[0] & 0x1);\n"//UIE=UPIE
7272 "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[65];\n"//PC=UEPC
7273 "((RISCV64*)cpu)->CSR[768]= ((RISCV64*)cpu)->CSR[0];\n"//keep MSTATUS synchronous to USTATUS
7274 "((RISCV64*)cpu)->CSR[256]=((RISCV64*)cpu)->CSR[0];\n"//keep SSTATUS synchronous to USTATUS
7275 
7276  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
7277 
7278  "return 0;\n"
7279 ;
7280 return true;
7281 },
7282 0,
7283 nullptr
7284 );
7285 //-------------------------------------------------------------------------------------------------------------------
7286 static InstructionDefinition fadd_s_rd_frs1_frs2(
7287  ISA32_RISCV64,
7288  "fadd.s",
7289  (uint32_t)0x53,
7290  (uint32_t) 0xfe00007f,
7291  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7292  {
7293  etiss_uint64 rs2 = 0;
7294  static BitArrayRange R_rs2_0 (24,20);
7295  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7296  rs2 += rs2_0;
7297  etiss_uint64 rs1 = 0;
7298  static BitArrayRange R_rs1_0 (19,15);
7299  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7300  rs1 += rs1_0;
7301  etiss_uint64 rd = 0;
7302  static BitArrayRange R_rd_0 (11,7);
7303  etiss_uint64 rd_0 = R_rd_0.read(ba);
7304  rd += rd_0;
7305  etiss_uint64 rm = 0;
7306  static BitArrayRange R_rm_0 (14,12);
7307  etiss_uint64 rm_0 = R_rm_0.read(ba);
7308  rm += rm_0;
7309  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7310  partInit.getAffectedRegisters().add(reg_name[rd],64);
7311  partInit.getAffectedRegisters().add("instructionPointer",64);
7312  partInit.code() = std::string("//fadd.s\n")+
7313  "etiss_uint32 temp = 0;\n"
7314  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7315  #if RISCV64_Pipeline1
7316  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7317  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7318  "etiss_uint32 num_stages = 4;\n"
7319  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7320  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7321  #endif
7322  #if RISCV64_Pipeline2
7323  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7324  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7325  "etiss_uint32 num_stages = 4;\n"
7326  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7327  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7328  #endif
7329 
7330  "etiss_uint32 res = 0;\n"
7331  "etiss_int64 upper = 0;\n"
7332  "etiss_uint32 flags = 0;\n"
7333  "etiss_uint32 frs1 = 0;\n"
7334  "etiss_uint32 choose1 = 0;\n"
7335  "etiss_uint32 frs2 = 0;\n"
7336 
7337 "if(64 == 32)\n"
7338 "{\n"
7339  "if(" + toString(rm) + " < 7)\n"
7340  "{\n"
7341  "choose1 = (" + toString(rm) + " & 0xff);\n"
7342  #if RISCV64_DEBUG_CALL
7343  "printf(\"choose1 = %#x\\n\",choose1); \n"
7344  #endif
7345  "}\n"
7346 
7347  "else\n"
7348  "{\n"
7349  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
7350  #if RISCV64_DEBUG_CALL
7351  "printf(\"choose1 = %#x\\n\",choose1); \n"
7352  #endif
7353  "}\n"
7354  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], choose1);\n"
7355  #if RISCV64_DEBUG_CALL
7356  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
7357  #endif
7358 "}\n"
7359 
7360 "else\n"
7361 "{\n"
7362  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
7363  #if RISCV64_DEBUG_CALL
7364  "printf(\"frs1 = %#x\\n\",frs1); \n"
7365  #endif
7366  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
7367  #if RISCV64_DEBUG_CALL
7368  "printf(\"frs2 = %#x\\n\",frs2); \n"
7369  #endif
7370  "if(" + toString(rm) + " < 7)\n"
7371  "{\n"
7372  "choose1 = (" + toString(rm) + " & 0xff);\n"
7373  #if RISCV64_DEBUG_CALL
7374  "printf(\"choose1 = %#x\\n\",choose1); \n"
7375  #endif
7376  "}\n"
7377 
7378  "else\n"
7379  "{\n"
7380  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
7381  #if RISCV64_DEBUG_CALL
7382  "printf(\"choose1 = %#x\\n\",choose1); \n"
7383  #endif
7384  "}\n"
7385  "res = fadd_s(frs1, frs2, choose1);\n"
7386  #if RISCV64_DEBUG_CALL
7387  "printf(\"res = %#x\\n\",res); \n"
7388  #endif
7389  "upper = - 1;\n"
7390  #if RISCV64_DEBUG_CALL
7391  "printf(\"upper = %#lx\\n\",upper); \n"
7392  #endif
7393  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
7394  #if RISCV64_DEBUG_CALL
7395  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
7396  #endif
7397 "}\n"
7398 "flags = fget_flags();\n"
7399 #if RISCV64_DEBUG_CALL
7400 "printf(\"flags = %#x\\n\",flags); \n"
7401 #endif
7402 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
7403 #if RISCV64_DEBUG_CALL
7404 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
7405 #endif
7406 
7407  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7408 
7409 ;
7410 return true;
7411 },
7412 0,
7413 nullptr
7414 );
7415 //-------------------------------------------------------------------------------------------------------------------
7416 static InstructionDefinition sub_rd_rs1_rs2(
7417  ISA32_RISCV64,
7418  "sub",
7419  (uint32_t)0x40000033,
7420  (uint32_t) 0xfe00707f,
7421  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7422  {
7423  etiss_uint64 rs2 = 0;
7424  static BitArrayRange R_rs2_0 (24,20);
7425  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7426  rs2 += rs2_0;
7427  etiss_uint64 rs1 = 0;
7428  static BitArrayRange R_rs1_0 (19,15);
7429  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7430  rs1 += rs1_0;
7431  etiss_uint64 rd = 0;
7432  static BitArrayRange R_rd_0 (11,7);
7433  etiss_uint64 rd_0 = R_rd_0.read(ba);
7434  rd += rd_0;
7435  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7436  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7437  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7438  partInit.getAffectedRegisters().add(reg_name[rd],64);
7439  partInit.getAffectedRegisters().add("instructionPointer",64);
7440  partInit.code() = std::string("//sub\n")+
7441  "etiss_uint32 temp = 0;\n"
7442  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7443  #if RISCV64_Pipeline1
7444  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7445  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7446  "etiss_uint32 num_stages = 4;\n"
7447  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7448  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7449  #endif
7450  #if RISCV64_Pipeline2
7451  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7452  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7453  "etiss_uint32 num_stages = 4;\n"
7454  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7455  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7456  #endif
7457 
7458 
7459 "if(" + toString(rd) + " != 0)\n"
7460 "{\n"
7461  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs1) + "] - *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
7462  #if RISCV64_DEBUG_CALL
7463  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7464  #endif
7465 "}\n"
7466 
7467 
7468  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7469 
7470 ;
7471 return true;
7472 },
7473 0,
7474 nullptr
7475 );
7476 //-------------------------------------------------------------------------------------------------------------------
7477 static InstructionDefinition subw_(
7478  ISA32_RISCV64,
7479  "subw",
7480  (uint32_t)0x4000003b,
7481  (uint32_t) 0xfe00707f,
7482  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7483  {
7484  etiss_uint64 rs2 = 0;
7485  static BitArrayRange R_rs2_0 (24,20);
7486  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7487  rs2 += rs2_0;
7488  etiss_uint64 rs1 = 0;
7489  static BitArrayRange R_rs1_0 (19,15);
7490  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7491  rs1 += rs1_0;
7492  etiss_uint64 rd = 0;
7493  static BitArrayRange R_rd_0 (11,7);
7494  etiss_uint64 rd_0 = R_rd_0.read(ba);
7495  rd += rd_0;
7496  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7497  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7498  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7499  partInit.getAffectedRegisters().add(reg_name[rd],64);
7500  partInit.getAffectedRegisters().add("instructionPointer",64);
7501  partInit.code() = std::string("//subw\n")+
7502  "etiss_uint32 temp = 0;\n"
7503  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7504  #if RISCV64_Pipeline1
7505  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7506  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7507  "etiss_uint32 num_stages = 4;\n"
7508  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7509  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7510  #endif
7511  #if RISCV64_Pipeline2
7512  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7513  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7514  "etiss_uint32 num_stages = 4;\n"
7515  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7516  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7517  #endif
7518 
7519  "etiss_uint32 res = 0;\n"
7520 
7521 "if(" + toString(rd) + " != 0)\n"
7522 "{\n"
7523  "res = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) - (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff);\n"
7524  #if RISCV64_DEBUG_CALL
7525  "printf(\"res = %#x\\n\",res); \n"
7526  #endif
7527  "etiss_int32 cast_0 = res; \n"
7528  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
7529  "{\n"
7530  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
7531  "}\n"
7532  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
7533  #if RISCV64_DEBUG_CALL
7534  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7535  #endif
7536 "}\n"
7537 
7538 
7539  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7540 
7541 ;
7542 return true;
7543 },
7544 0,
7545 nullptr
7546 );
7547 //-------------------------------------------------------------------------------------------------------------------
7548 static InstructionDefinition sra_rd_rs1_rs2(
7549  ISA32_RISCV64,
7550  "sra",
7551  (uint32_t)0x40005033,
7552  (uint32_t) 0xfe00707f,
7553  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7554  {
7555  etiss_uint64 rs2 = 0;
7556  static BitArrayRange R_rs2_0 (24,20);
7557  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7558  rs2 += rs2_0;
7559  etiss_uint64 rs1 = 0;
7560  static BitArrayRange R_rs1_0 (19,15);
7561  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7562  rs1 += rs1_0;
7563  etiss_uint64 rd = 0;
7564  static BitArrayRange R_rd_0 (11,7);
7565  etiss_uint64 rd_0 = R_rd_0.read(ba);
7566  rd += rd_0;
7567  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7568  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7569  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7570  partInit.getAffectedRegisters().add(reg_name[rd],64);
7571  partInit.getAffectedRegisters().add("instructionPointer",64);
7572  partInit.code() = std::string("//sra\n")+
7573  "etiss_uint32 temp = 0;\n"
7574  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7575  #if RISCV64_Pipeline1
7576  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7577  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7578  "etiss_uint32 num_stages = 4;\n"
7579  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7580  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7581  #endif
7582  #if RISCV64_Pipeline2
7583  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7584  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7585  "etiss_uint32 num_stages = 4;\n"
7586  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7587  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7588  #endif
7589 
7590 
7591 "if(" + toString(rd) + " != 0)\n"
7592 "{\n"
7593  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
7594  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
7595  "{\n"
7596  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
7597  "}\n"
7598  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 >> (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 64 - 1));\n"
7599  #if RISCV64_DEBUG_CALL
7600  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7601  #endif
7602 "}\n"
7603 
7604 
7605  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7606 
7607 ;
7608 return true;
7609 },
7610 0,
7611 nullptr
7612 );
7613 //-------------------------------------------------------------------------------------------------------------------
7614 static InstructionDefinition sraiw_rd_rs1_shamt(
7615  ISA32_RISCV64,
7616  "sraiw",
7617  (uint32_t)0x4000501b,
7618  (uint32_t) 0xfe00707f,
7619  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7620  {
7621  etiss_uint64 rs1 = 0;
7622  static BitArrayRange R_rs1_0 (19,15);
7623  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7624  rs1 += rs1_0;
7625  etiss_uint64 rd = 0;
7626  static BitArrayRange R_rd_0 (11,7);
7627  etiss_uint64 rd_0 = R_rd_0.read(ba);
7628  rd += rd_0;
7629  etiss_uint64 shamt = 0;
7630  static BitArrayRange R_shamt_0 (24,20);
7631  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
7632  shamt += shamt_0;
7633  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7634  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7635  partInit.getAffectedRegisters().add(reg_name[rd],64);
7636  partInit.getAffectedRegisters().add("instructionPointer",64);
7637  partInit.code() = std::string("//sraiw\n")+
7638  "etiss_uint32 temp = 0;\n"
7639  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7640  #if RISCV64_Pipeline1
7641  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7642  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7643  "etiss_uint32 num_stages = 4;\n"
7644  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7645  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7646  #endif
7647  #if RISCV64_Pipeline2
7648  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7649  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7650  "etiss_uint32 num_stages = 4;\n"
7651  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7652  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7653  #endif
7654 
7655  "etiss_int32 sh_val = 0;\n"
7656 
7657 "if(" + toString(rd) + " != 0)\n"
7658 "{\n"
7659  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
7660  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
7661  "{\n"
7662  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
7663  "}\n"
7664  "sh_val = ((etiss_int32)cast_0 >> " + toString(shamt) + ");\n"
7665  #if RISCV64_DEBUG_CALL
7666  "printf(\"sh_val = %#x\\n\",sh_val); \n"
7667  #endif
7668  "etiss_int32 cast_1 = sh_val; \n"
7669  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
7670  "{\n"
7671  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
7672  "}\n"
7673  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
7674  #if RISCV64_DEBUG_CALL
7675  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7676  #endif
7677 "}\n"
7678 
7679 
7680  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7681 
7682 ;
7683 return true;
7684 },
7685 0,
7686 nullptr
7687 );
7688 //-------------------------------------------------------------------------------------------------------------------
7689 static InstructionDefinition sraw_rd_rs1_rs2(
7690  ISA32_RISCV64,
7691  "sraw",
7692  (uint32_t)0x4000503b,
7693  (uint32_t) 0xfe00707f,
7694  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7695  {
7696  etiss_uint64 rs2 = 0;
7697  static BitArrayRange R_rs2_0 (24,20);
7698  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7699  rs2 += rs2_0;
7700  etiss_uint64 rs1 = 0;
7701  static BitArrayRange R_rs1_0 (19,15);
7702  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7703  rs1 += rs1_0;
7704  etiss_uint64 rd = 0;
7705  static BitArrayRange R_rd_0 (11,7);
7706  etiss_uint64 rd_0 = R_rd_0.read(ba);
7707  rd += rd_0;
7708  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7709  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7710  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7711  partInit.getAffectedRegisters().add(reg_name[rd],64);
7712  partInit.getAffectedRegisters().add("instructionPointer",64);
7713  partInit.code() = std::string("//sraw\n")+
7714  "etiss_uint32 temp = 0;\n"
7715  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7716  #if RISCV64_Pipeline1
7717  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7718  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7719  "etiss_uint32 num_stages = 4;\n"
7720  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7721  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7722  #endif
7723  #if RISCV64_Pipeline2
7724  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7725  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7726  "etiss_uint32 num_stages = 4;\n"
7727  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7728  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7729  #endif
7730 
7731  "etiss_uint32 sh_val = 0;\n"
7732  "etiss_uint32 count = 0;\n"
7733  "etiss_int32 mask = 0;\n"
7734 
7735 "if(" + toString(rd) + " != 0)\n"
7736 "{\n"
7737  "mask = 31;\n"
7738  #if RISCV64_DEBUG_CALL
7739  "printf(\"mask = %#x\\n\",mask); \n"
7740  #endif
7741  "count = ((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) & mask);\n"
7742  #if RISCV64_DEBUG_CALL
7743  "printf(\"count = %#x\\n\",count); \n"
7744  #endif
7745  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
7746  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
7747  "{\n"
7748  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
7749  "}\n"
7750  "sh_val = ((etiss_int32)cast_0 >> count);\n"
7751  #if RISCV64_DEBUG_CALL
7752  "printf(\"sh_val = %#x\\n\",sh_val); \n"
7753  #endif
7754  "etiss_int32 cast_1 = sh_val; \n"
7755  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
7756  "{\n"
7757  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
7758  "}\n"
7759  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
7760  #if RISCV64_DEBUG_CALL
7761  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7762  #endif
7763 "}\n"
7764 
7765 
7766  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7767 
7768 ;
7769 return true;
7770 },
7771 0,
7772 nullptr
7773 );
7774 //-------------------------------------------------------------------------------------------------------------------
7775 static InstructionDefinition fcvt_s_d_rd_frs1(
7776  ISA32_RISCV64,
7777  "fcvt.s.d",
7778  (uint32_t)0x40100053,
7779  (uint32_t) 0xfff0007f,
7780  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7781  {
7782  etiss_uint64 rs1 = 0;
7783  static BitArrayRange R_rs1_0 (19,15);
7784  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7785  rs1 += rs1_0;
7786  etiss_uint64 rd = 0;
7787  static BitArrayRange R_rd_0 (11,7);
7788  etiss_uint64 rd_0 = R_rd_0.read(ba);
7789  rd += rd_0;
7790  etiss_uint64 rm = 0;
7791  static BitArrayRange R_rm_0 (14,12);
7792  etiss_uint64 rm_0 = R_rm_0.read(ba);
7793  rm += rm_0;
7794  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7795  partInit.getAffectedRegisters().add(reg_name[rd],64);
7796  partInit.getAffectedRegisters().add("instructionPointer",64);
7797  partInit.code() = std::string("//fcvt.s.d\n")+
7798  "etiss_uint32 temp = 0;\n"
7799  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7800  #if RISCV64_Pipeline1
7801  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7802  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7803  "etiss_uint32 num_stages = 4;\n"
7804  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7805  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7806  #endif
7807  #if RISCV64_Pipeline2
7808  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7809  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7810  "etiss_uint32 num_stages = 4;\n"
7811  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7812  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7813  #endif
7814 
7815  "etiss_uint32 res = 0;\n"
7816  "etiss_int64 upper = 0;\n"
7817 
7818 "res = fconv_d2f(((RISCV64*)cpu)->F[" + toString(rs1) + "], (" + toString(rm) + " & 0xff));\n"
7819 #if RISCV64_DEBUG_CALL
7820 "printf(\"res = %#x\\n\",res); \n"
7821 #endif
7822 "upper = - 1;\n"
7823 #if RISCV64_DEBUG_CALL
7824 "printf(\"upper = %#lx\\n\",upper); \n"
7825 #endif
7826 "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
7827 #if RISCV64_DEBUG_CALL
7828 "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
7829 #endif
7830 
7831  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7832 
7833 ;
7834 return true;
7835 },
7836 0,
7837 nullptr
7838 );
7839 //-------------------------------------------------------------------------------------------------------------------
7840 static InstructionDefinition fence_(
7841  ISA32_RISCV64,
7842  "fence",
7843  (uint32_t)0xf,
7844  (uint32_t) 0xf000707f,
7845  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7846  {
7847  etiss_uint64 rs1 = 0;
7848  static BitArrayRange R_rs1_0 (19,15);
7849  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7850  rs1 += rs1_0;
7851  etiss_uint64 rd = 0;
7852  static BitArrayRange R_rd_0 (11,7);
7853  etiss_uint64 rd_0 = R_rd_0.read(ba);
7854  rd += rd_0;
7855  etiss_uint64 succ = 0;
7856  static BitArrayRange R_succ_0 (23,20);
7857  etiss_uint64 succ_0 = R_succ_0.read(ba);
7858  succ += succ_0;
7859  etiss_uint64 pred = 0;
7860  static BitArrayRange R_pred_0 (27,24);
7861  etiss_uint64 pred_0 = R_pred_0.read(ba);
7862  pred += pred_0;
7863  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7864  partInit.getAffectedRegisters().add(reg_name[0],64);
7865  partInit.getAffectedRegisters().add("instructionPointer",64);
7866  partInit.code() = std::string("//fence\n")+
7867  "etiss_uint32 temp = 0;\n"
7868  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7869  #if RISCV64_Pipeline1
7870  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7871  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7872  "etiss_uint32 num_stages = 4;\n"
7873  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7874  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7875  #endif
7876  #if RISCV64_Pipeline2
7877  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7878  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7879  "etiss_uint32 num_stages = 4;\n"
7880  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7881  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7882  #endif
7883 
7884 
7885 "((RISCV64*)cpu)->FENCE[0] = ((" + toString(pred) + " << 4) | " + toString(succ) + ");\n"
7886 #if RISCV64_DEBUG_CALL
7887 "printf(\"((RISCV64*)cpu)->FENCE[0] = %#lx\\n\",((RISCV64*)cpu)->FENCE[0]); \n"
7888 #endif
7889 
7890  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7891 
7892 ;
7893 return true;
7894 },
7895 0,
7896 nullptr
7897 );
7898 //-------------------------------------------------------------------------------------------------------------------
7899 static InstructionDefinition ecall_(
7900  ISA32_RISCV64,
7901  "ecall",
7902  (uint32_t)0x73,
7903  (uint32_t) 0xffffffff,
7904  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7905  {
7906  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7907  partInit.getAffectedRegisters().add("instructionPointer",64);
7908  partInit.code() = std::string("//ecall\n")+
7909  "etiss_uint32 exception = 0;\n"
7910  "etiss_uint32 temp = 0;\n"
7911  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7912  #if RISCV64_Pipeline1
7913  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7914  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7915  "etiss_uint32 num_stages = 4;\n"
7916  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7917  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7918  #endif
7919  #if RISCV64_Pipeline2
7920  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7921  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7922  "etiss_uint32 num_stages = 4;\n"
7923  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7924  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7925  #endif
7926 
7927 
7928 "exception = ETISS_RETURNCODE_SYSCALL; \n"
7929 
7930  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7931 
7932  "return exception;\n"
7933 ;
7934 return true;
7935 },
7936 0,
7937 nullptr
7938 );
7939 //-------------------------------------------------------------------------------------------------------------------
7940 static InstructionDefinition ebreak_(
7941  ISA32_RISCV64,
7942  "ebreak",
7943  (uint32_t)0x100073,
7944  (uint32_t) 0xffffffff,
7945  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7946  {
7947  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7948  partInit.getAffectedRegisters().add("instructionPointer",64);
7949  partInit.code() = std::string("//ebreak\n")+
7950  "etiss_uint32 exception = 0;\n"
7951  "etiss_uint32 temp = 0;\n"
7952  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7953  #if RISCV64_Pipeline1
7954  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7955  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7956  "etiss_uint32 num_stages = 4;\n"
7957  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7958  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7959  #endif
7960  #if RISCV64_Pipeline2
7961  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7962  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7963  "etiss_uint32 num_stages = 4;\n"
7964  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7965  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7966  #endif
7967 
7968 
7969 "return ETISS_RETURNCODE_CPUFINISHED; \n"
7970 
7971  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7972 
7973  "return exception;\n"
7974 ;
7975 return true;
7976 },
7977 0,
7978 nullptr
7979 );
7980 //-------------------------------------------------------------------------------------------------------------------
7981 static InstructionDefinition sret_(
7982  ISA32_RISCV64,
7983  "sret",
7984  (uint32_t)0x10200073,
7985  (uint32_t) 0xffffffff,
7986  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7987  {
7988  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7989  partInit.getAffectedRegisters().add("instructionPointer",64);
7990  partInit.code() = std::string("//sret\n")+
7991  "etiss_uint32 temp = 0;\n"
7992  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7993  #if RISCV64_Pipeline1
7994  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7995  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7996  "etiss_uint32 num_stages = 4;\n"
7997  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7998  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7999  #endif
8000  #if RISCV64_Pipeline2
8001  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8002  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8003  "etiss_uint32 num_stages = 4;\n"
8004  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8005  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8006  #endif
8007 
8008 
8009 "((RISCV64*)cpu)->CSR[3088] = (((RISCV64*)cpu)->CSR[256] & 0x100)>>8;\n"//PRIVLV=SPP
8010 "((RISCV64*)cpu)->CSR[256] ^= (((RISCV64*)cpu)->CSR[256] & 0x100);\n"//SPP=0
8011 "((RISCV64*)cpu)->CSR[256] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[256] & 0x20)>>4)) ^ (((RISCV64*)cpu)->CSR[256] & 0x2);\n"//SIE=SPIE
8012 "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[321];\n"//PC=SEPC
8013 "((RISCV64*)cpu)->CSR[768]= ((RISCV64*)cpu)->CSR[256];\n"//keep MSTATUS synchronous to SSTATUS
8014 "((RISCV64*)cpu)->CSR[0]=((RISCV64*)cpu)->CSR[256];\n"//keep USTATUS synchronous to SSTATUS
8015 
8016  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
8017 
8018  "return 0;\n"
8019 ;
8020 return true;
8021 },
8022 0,
8023 nullptr
8024 );
8025 //-------------------------------------------------------------------------------------------------------------------
8026 static InstructionDefinition wfi_(
8027  ISA32_RISCV64,
8028  "wfi",
8029  (uint32_t)0x10500073,
8030  (uint32_t) 0xffffffff,
8031  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8032  {
8033  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8034  partInit.getAffectedRegisters().add("instructionPointer",64);
8035  partInit.code() = std::string("//wfi\n")+
8036  "etiss_uint32 exception = 0;\n"
8037  "etiss_uint32 temp = 0;\n"
8038  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8039  #if RISCV64_Pipeline1
8040  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8041  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8042  "etiss_uint32 num_stages = 4;\n"
8043  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8044  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8045  #endif
8046  #if RISCV64_Pipeline2
8047  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8048  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8049  "etiss_uint32 num_stages = 4;\n"
8050  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8051  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8052  #endif
8053 
8054 
8055 "return ETISS_RETURNCODE_CPUFINISHED; \n"
8056 
8057  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8058 
8059  "return exception;\n"
8060 ;
8061 return true;
8062 },
8063 0,
8064 nullptr
8065 );
8066 //-------------------------------------------------------------------------------------------------------------------
8067 static InstructionDefinition fmul_s_rd_frs1_frs2(
8068  ISA32_RISCV64,
8069  "fmul.s",
8070  (uint32_t)0x10000053,
8071  (uint32_t) 0xfe00007f,
8072  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8073  {
8074  etiss_uint64 rs2 = 0;
8075  static BitArrayRange R_rs2_0 (24,20);
8076  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8077  rs2 += rs2_0;
8078  etiss_uint64 rs1 = 0;
8079  static BitArrayRange R_rs1_0 (19,15);
8080  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8081  rs1 += rs1_0;
8082  etiss_uint64 rd = 0;
8083  static BitArrayRange R_rd_0 (11,7);
8084  etiss_uint64 rd_0 = R_rd_0.read(ba);
8085  rd += rd_0;
8086  etiss_uint64 rm = 0;
8087  static BitArrayRange R_rm_0 (14,12);
8088  etiss_uint64 rm_0 = R_rm_0.read(ba);
8089  rm += rm_0;
8090  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8091  partInit.getAffectedRegisters().add(reg_name[rd],64);
8092  partInit.getAffectedRegisters().add("instructionPointer",64);
8093  partInit.code() = std::string("//fmul.s\n")+
8094  "etiss_uint32 temp = 0;\n"
8095  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8096  #if RISCV64_Pipeline1
8097  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8098  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8099  "etiss_uint32 num_stages = 4;\n"
8100  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8101  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8102  #endif
8103  #if RISCV64_Pipeline2
8104  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8105  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8106  "etiss_uint32 num_stages = 4;\n"
8107  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8108  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8109  #endif
8110 
8111  "etiss_uint32 res = 0;\n"
8112  "etiss_int64 upper = 0;\n"
8113  "etiss_uint32 flags = 0;\n"
8114  "etiss_uint32 frs1 = 0;\n"
8115  "etiss_uint32 choose1 = 0;\n"
8116  "etiss_uint32 frs2 = 0;\n"
8117 
8118 "if(64 == 32)\n"
8119 "{\n"
8120  "if(" + toString(rm) + " < 7)\n"
8121  "{\n"
8122  "choose1 = (" + toString(rm) + " & 0xff);\n"
8123  #if RISCV64_DEBUG_CALL
8124  "printf(\"choose1 = %#x\\n\",choose1); \n"
8125  #endif
8126  "}\n"
8127 
8128  "else\n"
8129  "{\n"
8130  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
8131  #if RISCV64_DEBUG_CALL
8132  "printf(\"choose1 = %#x\\n\",choose1); \n"
8133  #endif
8134  "}\n"
8135  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmul_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], choose1);\n"
8136  #if RISCV64_DEBUG_CALL
8137  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
8138  #endif
8139 "}\n"
8140 
8141 "else\n"
8142 "{\n"
8143  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
8144  #if RISCV64_DEBUG_CALL
8145  "printf(\"frs1 = %#x\\n\",frs1); \n"
8146  #endif
8147  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
8148  #if RISCV64_DEBUG_CALL
8149  "printf(\"frs2 = %#x\\n\",frs2); \n"
8150  #endif
8151  "if(" + toString(rm) + " < 7)\n"
8152  "{\n"
8153  "choose1 = (" + toString(rm) + " & 0xff);\n"
8154  #if RISCV64_DEBUG_CALL
8155  "printf(\"choose1 = %#x\\n\",choose1); \n"
8156  #endif
8157  "}\n"
8158 
8159  "else\n"
8160  "{\n"
8161  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
8162  #if RISCV64_DEBUG_CALL
8163  "printf(\"choose1 = %#x\\n\",choose1); \n"
8164  #endif
8165  "}\n"
8166  "res = fmul_s(frs1, frs2, choose1);\n"
8167  #if RISCV64_DEBUG_CALL
8168  "printf(\"res = %#x\\n\",res); \n"
8169  #endif
8170  "upper = - 1;\n"
8171  #if RISCV64_DEBUG_CALL
8172  "printf(\"upper = %#lx\\n\",upper); \n"
8173  #endif
8174  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
8175  #if RISCV64_DEBUG_CALL
8176  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
8177  #endif
8178 "}\n"
8179 "flags = fget_flags();\n"
8180 #if RISCV64_DEBUG_CALL
8181 "printf(\"flags = %#x\\n\",flags); \n"
8182 #endif
8183 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
8184 #if RISCV64_DEBUG_CALL
8185 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
8186 #endif
8187 
8188  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8189 
8190 ;
8191 return true;
8192 },
8193 0,
8194 nullptr
8195 );
8196 //-------------------------------------------------------------------------------------------------------------------
8197 static InstructionDefinition mret_(
8198  ISA32_RISCV64,
8199  "mret",
8200  (uint32_t)0x30200073,
8201  (uint32_t) 0xffffffff,
8202  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8203  {
8204  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8205  partInit.getAffectedRegisters().add("instructionPointer",64);
8206  partInit.code() = std::string("//mret\n")+
8207  "etiss_uint32 temp = 0;\n"
8208  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8209  #if RISCV64_Pipeline1
8210  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8211  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8212  "etiss_uint32 num_stages = 4;\n"
8213  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8214  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8215  #endif
8216  #if RISCV64_Pipeline2
8217  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8218  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8219  "etiss_uint32 num_stages = 4;\n"
8220  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8221  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8222  #endif
8223 
8224 
8225 "((RISCV64*)cpu)->CSR[3088] = (((RISCV64*)cpu)->CSR[768] & 0x1800)>>11;\n"//PRIVLV=MPP
8226 "((RISCV64*)cpu)->CSR[768] ^= (((RISCV64*)cpu)->CSR[768] & 0x1800);\n"//MPP=0
8227 "((RISCV64*)cpu)->CSR[768] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[768] & 0x80)>>4)) ^ (((RISCV64*)cpu)->CSR[768] & 0x8);\n"//MIE=MPIE
8228 "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[833];\n"//PC=MEPC
8229 "((RISCV64*)cpu)->CSR[0]= ((RISCV64*)cpu)->CSR[768];\n"//keep USTATUS synchronous to MSTATUS
8230 "((RISCV64*)cpu)->CSR[256]=((RISCV64*)cpu)->CSR[768];\n"//keep SSTATUS synchronous to MSTATUS
8231 
8232  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
8233 
8234  "return 0;\n"
8235 ;
8236 return true;
8237 },
8238 0,
8239 nullptr
8240 );
8241 //-------------------------------------------------------------------------------------------------------------------
8242 static InstructionDefinition sfence_vma_(
8243  ISA32_RISCV64,
8244  "sfence.vma",
8245  (uint32_t)0x12000073,
8246  (uint32_t) 0xfe007fff,
8247  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8248  {
8249  etiss_uint64 rs2 = 0;
8250  static BitArrayRange R_rs2_0 (24,20);
8251  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8252  rs2 += rs2_0;
8253  etiss_uint64 rs1 = 0;
8254  static BitArrayRange R_rs1_0 (19,15);
8255  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8256  rs1 += rs1_0;
8257  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8258  partInit.getAffectedRegisters().add(reg_name[2],64);
8259  partInit.getAffectedRegisters().add(reg_name[3],64);
8260  partInit.getAffectedRegisters().add("instructionPointer",64);
8261  partInit.code() = std::string("//sfence.vma\n")+
8262  "etiss_uint32 temp = 0;\n"
8263  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8264  #if RISCV64_Pipeline1
8265  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8266  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8267  "etiss_uint32 num_stages = 4;\n"
8268  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8269  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8270  #endif
8271  #if RISCV64_Pipeline2
8272  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8273  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8274  "etiss_uint32 num_stages = 4;\n"
8275  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8276  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8277  #endif
8278 
8279 
8280 "((RISCV64*)cpu)->FENCE[2] = " + toString(rs1) + ";\n"
8281 #if RISCV64_DEBUG_CALL
8282 "printf(\"((RISCV64*)cpu)->FENCE[2] = %#lx\\n\",((RISCV64*)cpu)->FENCE[2]); \n"
8283 #endif
8284 "((RISCV64*)cpu)->FENCE[3] = " + toString(rs2) + ";\n"
8285 #if RISCV64_DEBUG_CALL
8286 "printf(\"((RISCV64*)cpu)->FENCE[3] = %#lx\\n\",((RISCV64*)cpu)->FENCE[3]); \n"
8287 #endif
8288 
8289  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8290 
8291 ;
8292 return true;
8293 },
8294 0,
8295 nullptr
8296 );
8297 //-------------------------------------------------------------------------------------------------------------------
8298 static InstructionDefinition fmul_d_rd_frs1_frs2(
8299  ISA32_RISCV64,
8300  "fmul.d",
8301  (uint32_t)0x12000053,
8302  (uint32_t) 0xfe00007f,
8303  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8304  {
8305  etiss_uint64 rs2 = 0;
8306  static BitArrayRange R_rs2_0 (24,20);
8307  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8308  rs2 += rs2_0;
8309  etiss_uint64 rs1 = 0;
8310  static BitArrayRange R_rs1_0 (19,15);
8311  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8312  rs1 += rs1_0;
8313  etiss_uint64 rd = 0;
8314  static BitArrayRange R_rd_0 (11,7);
8315  etiss_uint64 rd_0 = R_rd_0.read(ba);
8316  rd += rd_0;
8317  etiss_uint64 rm = 0;
8318  static BitArrayRange R_rm_0 (14,12);
8319  etiss_uint64 rm_0 = R_rm_0.read(ba);
8320  rm += rm_0;
8321  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8322  partInit.getAffectedRegisters().add(reg_name[rd],64);
8323  partInit.getAffectedRegisters().add("instructionPointer",64);
8324  partInit.code() = std::string("//fmul.d\n")+
8325  "etiss_uint32 temp = 0;\n"
8326  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8327  #if RISCV64_Pipeline1
8328  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8329  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8330  "etiss_uint32 num_stages = 4;\n"
8331  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8332  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8333  #endif
8334  #if RISCV64_Pipeline2
8335  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8336  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8337  "etiss_uint32 num_stages = 4;\n"
8338  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8339  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8340  #endif
8341 
8342  "etiss_uint64 res = 0;\n"
8343  "etiss_int64 upper = 0;\n"
8344  "etiss_uint32 flags = 0;\n"
8345  "etiss_uint32 choose1 = 0;\n"
8346 
8347 "if(" + toString(rm) + " < 7)\n"
8348 "{\n"
8349  "choose1 = (" + toString(rm) + " & 0xff);\n"
8350  #if RISCV64_DEBUG_CALL
8351  "printf(\"choose1 = %#x\\n\",choose1); \n"
8352  #endif
8353 "}\n"
8354 
8355 "else\n"
8356 "{\n"
8357  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
8358  #if RISCV64_DEBUG_CALL
8359  "printf(\"choose1 = %#x\\n\",choose1); \n"
8360  #endif
8361 "}\n"
8362 "res = fmul_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n"
8363 #if RISCV64_DEBUG_CALL
8364 "printf(\"res = %#lx\\n\",res); \n"
8365 #endif
8366 "if(64 == 64)\n"
8367 "{\n"
8368  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
8369  #if RISCV64_DEBUG_CALL
8370  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
8371  #endif
8372 "}\n"
8373 
8374 "else\n"
8375 "{\n"
8376  "upper = - 1;\n"
8377  #if RISCV64_DEBUG_CALL
8378  "printf(\"upper = %#lx\\n\",upper); \n"
8379  #endif
8380  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
8381  #if RISCV64_DEBUG_CALL
8382  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
8383  #endif
8384 "}\n"
8385 "flags = fget_flags();\n"
8386 #if RISCV64_DEBUG_CALL
8387 "printf(\"flags = %#x\\n\",flags); \n"
8388 #endif
8389 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
8390 #if RISCV64_DEBUG_CALL
8391 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
8392 #endif
8393 
8394  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8395 
8396 ;
8397 return true;
8398 },
8399 0,
8400 nullptr
8401 );
8402 //-------------------------------------------------------------------------------------------------------------------
8403 static InstructionDefinition mul_rd_rs1_rs2(
8404  ISA32_RISCV64,
8405  "mul",
8406  (uint32_t)0x2000033,
8407  (uint32_t) 0xfe00707f,
8408  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8409  {
8410  etiss_uint64 rs2 = 0;
8411  static BitArrayRange R_rs2_0 (24,20);
8412  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8413  rs2 += rs2_0;
8414  etiss_uint64 rs1 = 0;
8415  static BitArrayRange R_rs1_0 (19,15);
8416  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8417  rs1 += rs1_0;
8418  etiss_uint64 rd = 0;
8419  static BitArrayRange R_rd_0 (11,7);
8420  etiss_uint64 rd_0 = R_rd_0.read(ba);
8421  rd += rd_0;
8422  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8423  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8424  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8425  partInit.getAffectedRegisters().add(reg_name[rd],64);
8426  partInit.getAffectedRegisters().add("instructionPointer",64);
8427  partInit.code() = std::string("//mul\n")+
8428  "etiss_uint32 temp = 0;\n"
8429  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8430  #if RISCV64_Pipeline1
8431  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8432  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {3}, {6, 7}};\n"
8433  "etiss_uint32 num_stages = 4;\n"
8434  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8435  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8436  #endif
8437  #if RISCV64_Pipeline2
8438  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8439  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {8}, {6, 7}};\n"
8440  "etiss_uint32 num_stages = 4;\n"
8441  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8442  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8443  #endif
8444 
8445  "etiss_uint64 res = 0;\n"
8446 
8447 "if(" + toString(rd) + " != 0)\n"
8448 "{\n"
8449  "res = ((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "] * (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
8450  #if RISCV64_DEBUG_CALL
8451  "printf(\"res = %#lx\\n\",res); \n"
8452  #endif
8453  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)res;\n"
8454  #if RISCV64_DEBUG_CALL
8455  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8456  #endif
8457 "}\n"
8458 
8459 
8460  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8461 
8462 ;
8463 return true;
8464 },
8465 0,
8466 nullptr
8467 );
8468 //-------------------------------------------------------------------------------------------------------------------
8469 static InstructionDefinition mulw_rd_rs1_rs2(
8470  ISA32_RISCV64,
8471  "mulw",
8472  (uint32_t)0x200003b,
8473  (uint32_t) 0xfe00707f,
8474  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8475  {
8476  etiss_uint64 rs2 = 0;
8477  static BitArrayRange R_rs2_0 (24,20);
8478  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8479  rs2 += rs2_0;
8480  etiss_uint64 rs1 = 0;
8481  static BitArrayRange R_rs1_0 (19,15);
8482  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8483  rs1 += rs1_0;
8484  etiss_uint64 rd = 0;
8485  static BitArrayRange R_rd_0 (11,7);
8486  etiss_uint64 rd_0 = R_rd_0.read(ba);
8487  rd += rd_0;
8488  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8489  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8490  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8491  partInit.getAffectedRegisters().add(reg_name[rd],64);
8492  partInit.getAffectedRegisters().add("instructionPointer",64);
8493  partInit.code() = std::string("//mulw\n")+
8494  "etiss_uint32 temp = 0;\n"
8495  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8496  #if RISCV64_Pipeline1
8497  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8498  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8499  "etiss_uint32 num_stages = 4;\n"
8500  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8501  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8502  #endif
8503  #if RISCV64_Pipeline2
8504  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8505  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8506  "etiss_uint32 num_stages = 4;\n"
8507  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8508  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8509  #endif
8510 
8511 
8512 "if(" + toString(rd) + " != 0)\n"
8513 "{\n"
8514  "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) * (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff)); \n"
8515  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8516  "{\n"
8517  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8518  "}\n"
8519  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
8520  #if RISCV64_DEBUG_CALL
8521  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8522  #endif
8523 "}\n"
8524 
8525 
8526  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8527 
8528 ;
8529 return true;
8530 },
8531 0,
8532 nullptr
8533 );
8534 //-------------------------------------------------------------------------------------------------------------------
8535 static InstructionDefinition mulh_rd_rs1_rs2(
8536  ISA32_RISCV64,
8537  "mulh",
8538  (uint32_t)0x2001033,
8539  (uint32_t) 0xfe00707f,
8540  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8541  {
8542  etiss_uint64 rs2 = 0;
8543  static BitArrayRange R_rs2_0 (24,20);
8544  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8545  rs2 += rs2_0;
8546  etiss_uint64 rs1 = 0;
8547  static BitArrayRange R_rs1_0 (19,15);
8548  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8549  rs1 += rs1_0;
8550  etiss_uint64 rd = 0;
8551  static BitArrayRange R_rd_0 (11,7);
8552  etiss_uint64 rd_0 = R_rd_0.read(ba);
8553  rd += rd_0;
8554  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8555  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8556  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8557  partInit.getAffectedRegisters().add(reg_name[rd],64);
8558  partInit.getAffectedRegisters().add("instructionPointer",64);
8559  partInit.code() = std::string("//mulh\n")+
8560  "etiss_uint32 temp = 0;\n"
8561  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8562  #if RISCV64_Pipeline1
8563  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8564  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8565  "etiss_uint32 num_stages = 4;\n"
8566  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8567  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8568  #endif
8569  #if RISCV64_Pipeline2
8570  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8571  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8572  "etiss_uint32 num_stages = 4;\n"
8573  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8574  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8575  #endif
8576 
8577  "etiss_int64 res = 0;\n"
8578 
8579 "if(" + toString(rd) + " != 0)\n"
8580 "{\n"
8581  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
8582  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8583  "{\n"
8584  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8585  "}\n"
8586  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
8587  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
8588  "{\n"
8589  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
8590  "}\n"
8591  "res = ((etiss_int64)cast_1 * (etiss_int64)cast_0);\n"
8592  #if RISCV64_DEBUG_CALL
8593  "printf(\"res = %#lx\\n\",res); \n"
8594  #endif
8595  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(res >> 64);\n"
8596  #if RISCV64_DEBUG_CALL
8597  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8598  #endif
8599 "}\n"
8600 
8601 
8602  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8603 
8604 ;
8605 return true;
8606 },
8607 0,
8608 nullptr
8609 );
8610 //-------------------------------------------------------------------------------------------------------------------
8611 static InstructionDefinition mulhsu_rd_rs1_rs2(
8612  ISA32_RISCV64,
8613  "mulhsu",
8614  (uint32_t)0x2002033,
8615  (uint32_t) 0xfe00707f,
8616  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8617  {
8618  etiss_uint64 rs2 = 0;
8619  static BitArrayRange R_rs2_0 (24,20);
8620  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8621  rs2 += rs2_0;
8622  etiss_uint64 rs1 = 0;
8623  static BitArrayRange R_rs1_0 (19,15);
8624  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8625  rs1 += rs1_0;
8626  etiss_uint64 rd = 0;
8627  static BitArrayRange R_rd_0 (11,7);
8628  etiss_uint64 rd_0 = R_rd_0.read(ba);
8629  rd += rd_0;
8630  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8631  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8632  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8633  partInit.getAffectedRegisters().add(reg_name[rd],64);
8634  partInit.getAffectedRegisters().add("instructionPointer",64);
8635  partInit.code() = std::string("//mulhsu\n")+
8636  "etiss_uint32 temp = 0;\n"
8637  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8638  #if RISCV64_Pipeline1
8639  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8640  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8641  "etiss_uint32 num_stages = 4;\n"
8642  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8643  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8644  #endif
8645  #if RISCV64_Pipeline2
8646  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8647  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8648  "etiss_uint32 num_stages = 4;\n"
8649  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8650  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8651  #endif
8652 
8653  "etiss_uint64 res = 0;\n"
8654 
8655 "if(" + toString(rd) + " != 0)\n"
8656 "{\n"
8657  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
8658  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8659  "{\n"
8660  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8661  "}\n"
8662  "res = ((etiss_int64)cast_0 * (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
8663  #if RISCV64_DEBUG_CALL
8664  "printf(\"res = %#lx\\n\",res); \n"
8665  #endif
8666  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(res >> 64);\n"
8667  #if RISCV64_DEBUG_CALL
8668  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8669  #endif
8670 "}\n"
8671 
8672 
8673  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8674 
8675 ;
8676 return true;
8677 },
8678 0,
8679 nullptr
8680 );
8681 //-------------------------------------------------------------------------------------------------------------------
8682 static InstructionDefinition mulhu_rd_rs1_rs2(
8683  ISA32_RISCV64,
8684  "mulhu",
8685  (uint32_t)0x2003033,
8686  (uint32_t) 0xfe00707f,
8687  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8688  {
8689  etiss_uint64 rs2 = 0;
8690  static BitArrayRange R_rs2_0 (24,20);
8691  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8692  rs2 += rs2_0;
8693  etiss_uint64 rs1 = 0;
8694  static BitArrayRange R_rs1_0 (19,15);
8695  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8696  rs1 += rs1_0;
8697  etiss_uint64 rd = 0;
8698  static BitArrayRange R_rd_0 (11,7);
8699  etiss_uint64 rd_0 = R_rd_0.read(ba);
8700  rd += rd_0;
8701  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8702  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8703  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8704  partInit.getAffectedRegisters().add(reg_name[rd],64);
8705  partInit.getAffectedRegisters().add("instructionPointer",64);
8706  partInit.code() = std::string("//mulhu\n")+
8707  "etiss_uint32 temp = 0;\n"
8708  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8709  #if RISCV64_Pipeline1
8710  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8711  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8712  "etiss_uint32 num_stages = 4;\n"
8713  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8714  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8715  #endif
8716  #if RISCV64_Pipeline2
8717  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8718  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8719  "etiss_uint32 num_stages = 4;\n"
8720  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8721  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8722  #endif
8723 
8724  "etiss_uint64 res = 0;\n"
8725 
8726 "if(" + toString(rd) + " != 0)\n"
8727 "{\n"
8728  "res = ((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "] * (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
8729  #if RISCV64_DEBUG_CALL
8730  "printf(\"res = %#lx\\n\",res); \n"
8731  #endif
8732  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(res >> 64);\n"
8733  #if RISCV64_DEBUG_CALL
8734  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8735  #endif
8736 "}\n"
8737 
8738 
8739  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8740 
8741 ;
8742 return true;
8743 },
8744 0,
8745 nullptr
8746 );
8747 //-------------------------------------------------------------------------------------------------------------------
8748 static InstructionDefinition div_rd_rs1_rs2(
8749  ISA32_RISCV64,
8750  "div",
8751  (uint32_t)0x2004033,
8752  (uint32_t) 0xfe00707f,
8753  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8754  {
8755  etiss_uint64 rs2 = 0;
8756  static BitArrayRange R_rs2_0 (24,20);
8757  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8758  rs2 += rs2_0;
8759  etiss_uint64 rs1 = 0;
8760  static BitArrayRange R_rs1_0 (19,15);
8761  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8762  rs1 += rs1_0;
8763  etiss_uint64 rd = 0;
8764  static BitArrayRange R_rd_0 (11,7);
8765  etiss_uint64 rd_0 = R_rd_0.read(ba);
8766  rd += rd_0;
8767  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8768  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8769  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8770  partInit.getAffectedRegisters().add(reg_name[rd],64);
8771  partInit.getAffectedRegisters().add("instructionPointer",64);
8772  partInit.code() = std::string("//div\n")+
8773  "etiss_uint32 temp = 0;\n"
8774  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8775  #if RISCV64_Pipeline1
8776  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8777  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8778  "etiss_uint32 num_stages = 4;\n"
8779  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8780  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8781  #endif
8782  #if RISCV64_Pipeline2
8783  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8784  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8785  "etiss_uint32 num_stages = 4;\n"
8786  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8787  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8788  #endif
8789 
8790  "etiss_int8 XLM1 = 0;\n"
8791  "etiss_int64 MMIN = 0;\n"
8792  "etiss_int64 M1 = 0;\n"
8793  "etiss_int64 ONE = 0;\n"
8794 
8795 "if(" + toString(rd) + " != 0)\n"
8796 "{\n"
8797  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
8798  "{\n"
8799  "M1 = - 1;\n"
8800  #if RISCV64_DEBUG_CALL
8801  "printf(\"M1 = %#lx\\n\",M1); \n"
8802  #endif
8803  "XLM1 = 64 - 1;\n"
8804  #if RISCV64_DEBUG_CALL
8805  "printf(\"XLM1 = %#x\\n\",XLM1); \n"
8806  #endif
8807  "ONE = 1;\n"
8808  #if RISCV64_DEBUG_CALL
8809  "printf(\"ONE = %#lx\\n\",ONE); \n"
8810  #endif
8811  "MMIN = (ONE << XLM1);\n"
8812  #if RISCV64_DEBUG_CALL
8813  "printf(\"MMIN = %#lx\\n\",MMIN); \n"
8814  #endif
8815  "if((*((RISCV64*)cpu)->X[" + toString(rs1) + "] == MMIN) && (*((RISCV64*)cpu)->X[" + toString(rs2) + "] == M1))\n"
8816  "{\n"
8817  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = MMIN;\n"
8818  #if RISCV64_DEBUG_CALL
8819  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8820  #endif
8821  "}\n"
8822 
8823  "else\n"
8824  "{\n"
8825  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
8826  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8827  "{\n"
8828  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8829  "}\n"
8830  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
8831  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
8832  "{\n"
8833  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
8834  "}\n"
8835  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_1 / (etiss_int64)cast_0);\n"
8836  #if RISCV64_DEBUG_CALL
8837  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8838  #endif
8839  "}\n"
8840  "}\n"
8841 
8842  "else\n"
8843  "{\n"
8844  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = - 1;\n"
8845  #if RISCV64_DEBUG_CALL
8846  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8847  #endif
8848  "}\n"
8849 "}\n"
8850 
8851 
8852  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8853 
8854 ;
8855 return true;
8856 },
8857 0,
8858 nullptr
8859 );
8860 //-------------------------------------------------------------------------------------------------------------------
8861 static InstructionDefinition divw_rd_rs1_rs2(
8862  ISA32_RISCV64,
8863  "divw",
8864  (uint32_t)0x200403b,
8865  (uint32_t) 0xfe00707f,
8866  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8867  {
8868  etiss_uint64 rs2 = 0;
8869  static BitArrayRange R_rs2_0 (24,20);
8870  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8871  rs2 += rs2_0;
8872  etiss_uint64 rs1 = 0;
8873  static BitArrayRange R_rs1_0 (19,15);
8874  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8875  rs1 += rs1_0;
8876  etiss_uint64 rd = 0;
8877  static BitArrayRange R_rd_0 (11,7);
8878  etiss_uint64 rd_0 = R_rd_0.read(ba);
8879  rd += rd_0;
8880  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8881  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8882  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8883  partInit.getAffectedRegisters().add(reg_name[rd],64);
8884  partInit.getAffectedRegisters().add("instructionPointer",64);
8885  partInit.code() = std::string("//divw\n")+
8886  "etiss_uint32 temp = 0;\n"
8887  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8888  #if RISCV64_Pipeline1
8889  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8890  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8891  "etiss_uint32 num_stages = 4;\n"
8892  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8893  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8894  #endif
8895  #if RISCV64_Pipeline2
8896  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8897  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8898  "etiss_uint32 num_stages = 4;\n"
8899  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8900  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8901  #endif
8902 
8903  "etiss_int32 MMIN = 0;\n"
8904  "etiss_int32 M1 = 0;\n"
8905  "etiss_int32 ONE = 0;\n"
8906 
8907 "if(" + toString(rd) + " != 0)\n"
8908 "{\n"
8909  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
8910  "{\n"
8911  "M1 = - 1;\n"
8912  #if RISCV64_DEBUG_CALL
8913  "printf(\"M1 = %#x\\n\",M1); \n"
8914  #endif
8915  "ONE = 1;\n"
8916  #if RISCV64_DEBUG_CALL
8917  "printf(\"ONE = %#x\\n\",ONE); \n"
8918  #endif
8919  "MMIN = (ONE << 31);\n"
8920  #if RISCV64_DEBUG_CALL
8921  "printf(\"MMIN = %#x\\n\",MMIN); \n"
8922  #endif
8923  "if(((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) == MMIN) && ((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) == M1))\n"
8924  "{\n"
8925  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ( - 1 << 31);\n"
8926  #if RISCV64_DEBUG_CALL
8927  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8928  #endif
8929  "}\n"
8930 
8931  "else\n"
8932  "{\n"
8933  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff); \n"
8934  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8935  "{\n"
8936  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8937  "}\n"
8938  "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
8939  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
8940  "{\n"
8941  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
8942  "}\n"
8943  "etiss_int64 cast_2 = ((etiss_int64)cast_1 / (etiss_int64)cast_0); \n"
8944  "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
8945  "{\n"
8946  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
8947  "}\n"
8948  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_2;\n"
8949  #if RISCV64_DEBUG_CALL
8950  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8951  #endif
8952  "}\n"
8953  "}\n"
8954 
8955  "else\n"
8956  "{\n"
8957  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = - 1;\n"
8958  #if RISCV64_DEBUG_CALL
8959  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8960  #endif
8961  "}\n"
8962 "}\n"
8963 
8964 
8965  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8966 
8967 ;
8968 return true;
8969 },
8970 0,
8971 nullptr
8972 );
8973 //-------------------------------------------------------------------------------------------------------------------
8974 static InstructionDefinition divu_rd_rs1_rs2(
8975  ISA32_RISCV64,
8976  "divu",
8977  (uint32_t)0x2005033,
8978  (uint32_t) 0xfe00707f,
8979  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8980  {
8981  etiss_uint64 rs2 = 0;
8982  static BitArrayRange R_rs2_0 (24,20);
8983  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8984  rs2 += rs2_0;
8985  etiss_uint64 rs1 = 0;
8986  static BitArrayRange R_rs1_0 (19,15);
8987  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8988  rs1 += rs1_0;
8989  etiss_uint64 rd = 0;
8990  static BitArrayRange R_rd_0 (11,7);
8991  etiss_uint64 rd_0 = R_rd_0.read(ba);
8992  rd += rd_0;
8993  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8994  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8995  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8996  partInit.getAffectedRegisters().add(reg_name[rd],64);
8997  partInit.getAffectedRegisters().add("instructionPointer",64);
8998  partInit.code() = std::string("//divu\n")+
8999  "etiss_uint32 temp = 0;\n"
9000  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9001  #if RISCV64_Pipeline1
9002  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9003  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9004  "etiss_uint32 num_stages = 4;\n"
9005  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9006  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9007  #endif
9008  #if RISCV64_Pipeline2
9009  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9010  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9011  "etiss_uint32 num_stages = 4;\n"
9012  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9013  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9014  #endif
9015 
9016 
9017 "if(" + toString(rd) + " != 0)\n"
9018 "{\n"
9019  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
9020  "{\n"
9021  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] / *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
9022  #if RISCV64_DEBUG_CALL
9023  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9024  #endif
9025  "}\n"
9026 
9027  "else\n"
9028  "{\n"
9029  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = - 1;\n"
9030  #if RISCV64_DEBUG_CALL
9031  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9032  #endif
9033  "}\n"
9034 "}\n"
9035 
9036 
9037  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9038 
9039 ;
9040 return true;
9041 },
9042 0,
9043 nullptr
9044 );
9045 //-------------------------------------------------------------------------------------------------------------------
9046 static InstructionDefinition divuw_rd_rs1_rs2(
9047  ISA32_RISCV64,
9048  "divuw",
9049  (uint32_t)0x200503b,
9050  (uint32_t) 0xfe00707f,
9051  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9052  {
9053  etiss_uint64 rs2 = 0;
9054  static BitArrayRange R_rs2_0 (24,20);
9055  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9056  rs2 += rs2_0;
9057  etiss_uint64 rs1 = 0;
9058  static BitArrayRange R_rs1_0 (19,15);
9059  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9060  rs1 += rs1_0;
9061  etiss_uint64 rd = 0;
9062  static BitArrayRange R_rd_0 (11,7);
9063  etiss_uint64 rd_0 = R_rd_0.read(ba);
9064  rd += rd_0;
9065  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9066  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9067  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9068  partInit.getAffectedRegisters().add(reg_name[rd],64);
9069  partInit.getAffectedRegisters().add("instructionPointer",64);
9070  partInit.code() = std::string("//divuw\n")+
9071  "etiss_uint32 temp = 0;\n"
9072  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9073  #if RISCV64_Pipeline1
9074  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9075  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9076  "etiss_uint32 num_stages = 4;\n"
9077  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9078  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9079  #endif
9080  #if RISCV64_Pipeline2
9081  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9082  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9083  "etiss_uint32 num_stages = 4;\n"
9084  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9085  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9086  #endif
9087 
9088 
9089 "if(" + toString(rd) + " != 0)\n"
9090 "{\n"
9091  "if((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) != 0)\n"
9092  "{\n"
9093  "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) / (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff)); \n"
9094  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9095  "{\n"
9096  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9097  "}\n"
9098  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
9099  #if RISCV64_DEBUG_CALL
9100  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9101  #endif
9102  "}\n"
9103 
9104  "else\n"
9105  "{\n"
9106  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = - 1;\n"
9107  #if RISCV64_DEBUG_CALL
9108  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9109  #endif
9110  "}\n"
9111 "}\n"
9112 
9113 
9114  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9115 
9116 ;
9117 return true;
9118 },
9119 0,
9120 nullptr
9121 );
9122 //-------------------------------------------------------------------------------------------------------------------
9123 static InstructionDefinition rem_rd_rs1_rs2(
9124  ISA32_RISCV64,
9125  "rem",
9126  (uint32_t)0x2006033,
9127  (uint32_t) 0xfe00707f,
9128  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9129  {
9130  etiss_uint64 rs2 = 0;
9131  static BitArrayRange R_rs2_0 (24,20);
9132  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9133  rs2 += rs2_0;
9134  etiss_uint64 rs1 = 0;
9135  static BitArrayRange R_rs1_0 (19,15);
9136  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9137  rs1 += rs1_0;
9138  etiss_uint64 rd = 0;
9139  static BitArrayRange R_rd_0 (11,7);
9140  etiss_uint64 rd_0 = R_rd_0.read(ba);
9141  rd += rd_0;
9142  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9143  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9144  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9145  partInit.getAffectedRegisters().add(reg_name[rd],64);
9146  partInit.getAffectedRegisters().add("instructionPointer",64);
9147  partInit.code() = std::string("//rem\n")+
9148  "etiss_uint32 temp = 0;\n"
9149  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9150  #if RISCV64_Pipeline1
9151  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9152  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9153  "etiss_uint32 num_stages = 4;\n"
9154  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9155  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9156  #endif
9157  #if RISCV64_Pipeline2
9158  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9159  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9160  "etiss_uint32 num_stages = 4;\n"
9161  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9162  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9163  #endif
9164 
9165  "etiss_int32 XLM1 = 0;\n"
9166  "etiss_int64 MMIN = 0;\n"
9167  "etiss_int64 M1 = 0;\n"
9168  "etiss_int64 ONE = 0;\n"
9169 
9170 "if(" + toString(rd) + " != 0)\n"
9171 "{\n"
9172  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
9173  "{\n"
9174  "M1 = - 1;\n"
9175  #if RISCV64_DEBUG_CALL
9176  "printf(\"M1 = %#lx\\n\",M1); \n"
9177  #endif
9178  "XLM1 = 64 - 1;\n"
9179  #if RISCV64_DEBUG_CALL
9180  "printf(\"XLM1 = %#x\\n\",XLM1); \n"
9181  #endif
9182  "ONE = 1;\n"
9183  #if RISCV64_DEBUG_CALL
9184  "printf(\"ONE = %#lx\\n\",ONE); \n"
9185  #endif
9186  "MMIN = (ONE << XLM1);\n"
9187  #if RISCV64_DEBUG_CALL
9188  "printf(\"MMIN = %#lx\\n\",MMIN); \n"
9189  #endif
9190  "if((*((RISCV64*)cpu)->X[" + toString(rs1) + "] == MMIN) && (*((RISCV64*)cpu)->X[" + toString(rs2) + "] == M1))\n"
9191  "{\n"
9192  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 0;\n"
9193  #if RISCV64_DEBUG_CALL
9194  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9195  #endif
9196  "}\n"
9197 
9198  "else\n"
9199  "{\n"
9200  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
9201  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9202  "{\n"
9203  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9204  "}\n"
9205  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
9206  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
9207  "{\n"
9208  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
9209  "}\n"
9210  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_1 % (etiss_int64)cast_0);\n"
9211  #if RISCV64_DEBUG_CALL
9212  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9213  #endif
9214  "}\n"
9215  "}\n"
9216 
9217  "else\n"
9218  "{\n"
9219  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9220  #if RISCV64_DEBUG_CALL
9221  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9222  #endif
9223  "}\n"
9224 "}\n"
9225 
9226 
9227  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9228 
9229 ;
9230 return true;
9231 },
9232 0,
9233 nullptr
9234 );
9235 //-------------------------------------------------------------------------------------------------------------------
9236 static InstructionDefinition remw_rd_rs1_rs2(
9237  ISA32_RISCV64,
9238  "remw",
9239  (uint32_t)0x200603b,
9240  (uint32_t) 0xfe00707f,
9241  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9242  {
9243  etiss_uint64 rs2 = 0;
9244  static BitArrayRange R_rs2_0 (24,20);
9245  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9246  rs2 += rs2_0;
9247  etiss_uint64 rs1 = 0;
9248  static BitArrayRange R_rs1_0 (19,15);
9249  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9250  rs1 += rs1_0;
9251  etiss_uint64 rd = 0;
9252  static BitArrayRange R_rd_0 (11,7);
9253  etiss_uint64 rd_0 = R_rd_0.read(ba);
9254  rd += rd_0;
9255  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9256  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9257  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9258  partInit.getAffectedRegisters().add(reg_name[rd],64);
9259  partInit.getAffectedRegisters().add("instructionPointer",64);
9260  partInit.code() = std::string("//remw\n")+
9261  "etiss_uint32 temp = 0;\n"
9262  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9263  #if RISCV64_Pipeline1
9264  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9265  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9266  "etiss_uint32 num_stages = 4;\n"
9267  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9268  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9269  #endif
9270  #if RISCV64_Pipeline2
9271  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9272  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9273  "etiss_uint32 num_stages = 4;\n"
9274  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9275  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9276  #endif
9277 
9278  "etiss_int32 MMIN = 0;\n"
9279  "etiss_int32 M1 = 0;\n"
9280  "etiss_int32 ONE = 0;\n"
9281 
9282 "if(" + toString(rd) + " != 0)\n"
9283 "{\n"
9284  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
9285  "{\n"
9286  "M1 = - 1;\n"
9287  #if RISCV64_DEBUG_CALL
9288  "printf(\"M1 = %#x\\n\",M1); \n"
9289  #endif
9290  "ONE = 1;\n"
9291  #if RISCV64_DEBUG_CALL
9292  "printf(\"ONE = %#x\\n\",ONE); \n"
9293  #endif
9294  "MMIN = (ONE << 31);\n"
9295  #if RISCV64_DEBUG_CALL
9296  "printf(\"MMIN = %#x\\n\",MMIN); \n"
9297  #endif
9298  "if(((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) == MMIN) && (*((RISCV64*)cpu)->X[" + toString(rs2) + "] == M1))\n"
9299  "{\n"
9300  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 0;\n"
9301  #if RISCV64_DEBUG_CALL
9302  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9303  #endif
9304  "}\n"
9305 
9306  "else\n"
9307  "{\n"
9308  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff); \n"
9309  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9310  "{\n"
9311  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9312  "}\n"
9313  "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
9314  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
9315  "{\n"
9316  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
9317  "}\n"
9318  "etiss_int64 cast_2 = ((etiss_int64)cast_1 % (etiss_int64)cast_0); \n"
9319  "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
9320  "{\n"
9321  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
9322  "}\n"
9323  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_2;\n"
9324  #if RISCV64_DEBUG_CALL
9325  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9326  #endif
9327  "}\n"
9328  "}\n"
9329 
9330  "else\n"
9331  "{\n"
9332  "etiss_int64 cast_3 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
9333  "if((etiss_int64)((etiss_uint64)cast_3 - 0x8000000000000000) > 0x0)\n"
9334  "{\n"
9335  "cast_3 =0x0 + (etiss_uint64)cast_3 ;\n"
9336  "}\n"
9337  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_3;\n"
9338  #if RISCV64_DEBUG_CALL
9339  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9340  #endif
9341  "}\n"
9342 "}\n"
9343 
9344 
9345  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9346 
9347 ;
9348 return true;
9349 },
9350 0,
9351 nullptr
9352 );
9353 //-------------------------------------------------------------------------------------------------------------------
9354 static InstructionDefinition remu_rd_rs1_rs2(
9355  ISA32_RISCV64,
9356  "remu",
9357  (uint32_t)0x2007033,
9358  (uint32_t) 0xfe00707f,
9359  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9360  {
9361  etiss_uint64 rs2 = 0;
9362  static BitArrayRange R_rs2_0 (24,20);
9363  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9364  rs2 += rs2_0;
9365  etiss_uint64 rs1 = 0;
9366  static BitArrayRange R_rs1_0 (19,15);
9367  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9368  rs1 += rs1_0;
9369  etiss_uint64 rd = 0;
9370  static BitArrayRange R_rd_0 (11,7);
9371  etiss_uint64 rd_0 = R_rd_0.read(ba);
9372  rd += rd_0;
9373  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9374  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9375  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9376  partInit.getAffectedRegisters().add(reg_name[rd],64);
9377  partInit.getAffectedRegisters().add("instructionPointer",64);
9378  partInit.code() = std::string("//remu\n")+
9379  "etiss_uint32 temp = 0;\n"
9380  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9381  #if RISCV64_Pipeline1
9382  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9383  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9384  "etiss_uint32 num_stages = 4;\n"
9385  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9386  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9387  #endif
9388  #if RISCV64_Pipeline2
9389  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9390  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9391  "etiss_uint32 num_stages = 4;\n"
9392  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9393  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9394  #endif
9395 
9396 
9397 "if(" + toString(rd) + " != 0)\n"
9398 "{\n"
9399  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
9400  "{\n"
9401  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] % *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
9402  #if RISCV64_DEBUG_CALL
9403  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9404  #endif
9405  "}\n"
9406 
9407  "else\n"
9408  "{\n"
9409  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9410  #if RISCV64_DEBUG_CALL
9411  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9412  #endif
9413  "}\n"
9414 "}\n"
9415 
9416 
9417  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9418 
9419 ;
9420 return true;
9421 },
9422 0,
9423 nullptr
9424 );
9425 //-------------------------------------------------------------------------------------------------------------------
9426 static InstructionDefinition remuw_rd_rs1_rs2(
9427  ISA32_RISCV64,
9428  "remuw",
9429  (uint32_t)0x200703b,
9430  (uint32_t) 0xfe00707f,
9431  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9432  {
9433  etiss_uint64 rs2 = 0;
9434  static BitArrayRange R_rs2_0 (24,20);
9435  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9436  rs2 += rs2_0;
9437  etiss_uint64 rs1 = 0;
9438  static BitArrayRange R_rs1_0 (19,15);
9439  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9440  rs1 += rs1_0;
9441  etiss_uint64 rd = 0;
9442  static BitArrayRange R_rd_0 (11,7);
9443  etiss_uint64 rd_0 = R_rd_0.read(ba);
9444  rd += rd_0;
9445  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9446  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9447  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9448  partInit.getAffectedRegisters().add(reg_name[rd],64);
9449  partInit.getAffectedRegisters().add("instructionPointer",64);
9450  partInit.code() = std::string("//remuw\n")+
9451  "etiss_uint32 temp = 0;\n"
9452  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9453  #if RISCV64_Pipeline1
9454  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9455  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9456  "etiss_uint32 num_stages = 4;\n"
9457  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9458  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9459  #endif
9460  #if RISCV64_Pipeline2
9461  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9462  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9463  "etiss_uint32 num_stages = 4;\n"
9464  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9465  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9466  #endif
9467 
9468 
9469 "if(" + toString(rd) + " != 0)\n"
9470 "{\n"
9471  "if((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) != 0)\n"
9472  "{\n"
9473  "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) % (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff)); \n"
9474  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9475  "{\n"
9476  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9477  "}\n"
9478  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
9479  #if RISCV64_DEBUG_CALL
9480  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9481  #endif
9482  "}\n"
9483 
9484  "else\n"
9485  "{\n"
9486  "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
9487  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
9488  "{\n"
9489  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
9490  "}\n"
9491  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
9492  #if RISCV64_DEBUG_CALL
9493  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9494  #endif
9495  "}\n"
9496 "}\n"
9497 
9498 
9499  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9500 
9501 ;
9502 return true;
9503 },
9504 0,
9505 nullptr
9506 );
9507 //-------------------------------------------------------------------------------------------------------------------
9508 static InstructionDefinition fadd_d_rd_frs1_frs2(
9509  ISA32_RISCV64,
9510  "fadd.d",
9511  (uint32_t)0x2000053,
9512  (uint32_t) 0xfe00007f,
9513  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9514  {
9515  etiss_uint64 rs2 = 0;
9516  static BitArrayRange R_rs2_0 (24,20);
9517  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9518  rs2 += rs2_0;
9519  etiss_uint64 rs1 = 0;
9520  static BitArrayRange R_rs1_0 (19,15);
9521  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9522  rs1 += rs1_0;
9523  etiss_uint64 rd = 0;
9524  static BitArrayRange R_rd_0 (11,7);
9525  etiss_uint64 rd_0 = R_rd_0.read(ba);
9526  rd += rd_0;
9527  etiss_uint64 rm = 0;
9528  static BitArrayRange R_rm_0 (14,12);
9529  etiss_uint64 rm_0 = R_rm_0.read(ba);
9530  rm += rm_0;
9531  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9532  partInit.getAffectedRegisters().add(reg_name[rd],64);
9533  partInit.getAffectedRegisters().add("instructionPointer",64);
9534  partInit.code() = std::string("//fadd.d\n")+
9535  "etiss_uint32 temp = 0;\n"
9536  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9537  #if RISCV64_Pipeline1
9538  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9539  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9540  "etiss_uint32 num_stages = 4;\n"
9541  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9542  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9543  #endif
9544  #if RISCV64_Pipeline2
9545  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9546  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9547  "etiss_uint32 num_stages = 4;\n"
9548  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9549  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9550  #endif
9551 
9552  "etiss_uint64 res = 0;\n"
9553  "etiss_int64 upper = 0;\n"
9554  "etiss_uint32 flags = 0;\n"
9555  "etiss_uint32 choose1 = 0;\n"
9556 
9557 "if(" + toString(rm) + " < 7)\n"
9558 "{\n"
9559  "choose1 = (" + toString(rm) + " & 0xff);\n"
9560  #if RISCV64_DEBUG_CALL
9561  "printf(\"choose1 = %#x\\n\",choose1); \n"
9562  #endif
9563 "}\n"
9564 
9565 "else\n"
9566 "{\n"
9567  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
9568  #if RISCV64_DEBUG_CALL
9569  "printf(\"choose1 = %#x\\n\",choose1); \n"
9570  #endif
9571 "}\n"
9572 "res = fadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n"
9573 #if RISCV64_DEBUG_CALL
9574 "printf(\"res = %#lx\\n\",res); \n"
9575 #endif
9576 "if(64 == 64)\n"
9577 "{\n"
9578  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
9579  #if RISCV64_DEBUG_CALL
9580  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
9581  #endif
9582 "}\n"
9583 
9584 "else\n"
9585 "{\n"
9586  "upper = - 1;\n"
9587  #if RISCV64_DEBUG_CALL
9588  "printf(\"upper = %#lx\\n\",upper); \n"
9589  #endif
9590  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
9591  #if RISCV64_DEBUG_CALL
9592  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
9593  #endif
9594 "}\n"
9595 "flags = fget_flags();\n"
9596 #if RISCV64_DEBUG_CALL
9597 "printf(\"flags = %#x\\n\",flags); \n"
9598 #endif
9599 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
9600 #if RISCV64_DEBUG_CALL
9601 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
9602 #endif
9603 
9604  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9605 
9606 ;
9607 return true;
9608 },
9609 0,
9610 nullptr
9611 );
9612 //-------------------------------------------------------------------------------------------------------------------
9613 static InstructionDefinition lr_w_rd_rs1(
9614  ISA32_RISCV64,
9615  "lr.w",
9616  (uint32_t)0x1000202f,
9617  (uint32_t) 0xf9f0707f,
9618  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9619  {
9620  etiss_uint64 aq = 0;
9621  static BitArrayRange R_aq_0 (26,26);
9622  etiss_uint64 aq_0 = R_aq_0.read(ba);
9623  aq += aq_0;
9624  etiss_uint64 rs1 = 0;
9625  static BitArrayRange R_rs1_0 (19,15);
9626  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9627  rs1 += rs1_0;
9628  etiss_uint64 rd = 0;
9629  static BitArrayRange R_rd_0 (11,7);
9630  etiss_uint64 rd_0 = R_rd_0.read(ba);
9631  rd += rd_0;
9632  etiss_uint64 rl = 0;
9633  static BitArrayRange R_rl_0 (25,25);
9634  etiss_uint64 rl_0 = R_rl_0.read(ba);
9635  rl += rl_0;
9636  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9637  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9638  partInit.getAffectedRegisters().add(reg_name[rd],64);
9639  partInit.getAffectedRegisters().add("instructionPointer",64);
9640  partInit.code() = std::string("//lr.w\n")+
9641  "etiss_uint32 exception = 0;\n"
9642  "etiss_uint32 temp = 0;\n"
9643  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9644  #if RISCV64_Pipeline1
9645  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9646  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9647  "etiss_uint32 num_stages = 4;\n"
9648  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9649  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9650  #endif
9651  #if RISCV64_Pipeline2
9652  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9653  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9654  "etiss_uint32 num_stages = 4;\n"
9655  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9656  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9657  #endif
9658 
9659  "etiss_uint64 offs = 0;\n"
9660 
9661 "if(" + toString(rd) + " != 0)\n"
9662 "{\n"
9663  "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9664  #if RISCV64_DEBUG_CALL
9665  "printf(\"offs = %#lx\\n\",offs); \n"
9666  #endif
9667  "etiss_uint32 MEM_offs;\n"
9668  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
9669  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
9670  "etiss_int32 cast_0 = MEM_offs; \n"
9671  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
9672  "{\n"
9673  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
9674  "}\n"
9675  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
9676  #if RISCV64_DEBUG_CALL
9677  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9678  #endif
9679  "((RISCV64*)cpu)->RES = offs;\n"
9680  #if RISCV64_DEBUG_CALL
9681  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9682  #endif
9683 "}\n"
9684 
9685 
9686  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9687 
9688  "return exception;\n"
9689 ;
9690 return true;
9691 },
9692 0,
9693 nullptr
9694 );
9695 //-------------------------------------------------------------------------------------------------------------------
9696 static InstructionDefinition lr_d_rd_rs1(
9697  ISA32_RISCV64,
9698  "lr.d",
9699  (uint32_t)0x1000302f,
9700  (uint32_t) 0xf9f0707f,
9701  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9702  {
9703  etiss_uint64 aq = 0;
9704  static BitArrayRange R_aq_0 (26,26);
9705  etiss_uint64 aq_0 = R_aq_0.read(ba);
9706  aq += aq_0;
9707  etiss_uint64 rs1 = 0;
9708  static BitArrayRange R_rs1_0 (19,15);
9709  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9710  rs1 += rs1_0;
9711  etiss_uint64 rd = 0;
9712  static BitArrayRange R_rd_0 (11,7);
9713  etiss_uint64 rd_0 = R_rd_0.read(ba);
9714  rd += rd_0;
9715  etiss_uint64 rl = 0;
9716  static BitArrayRange R_rl_0 (25,25);
9717  etiss_uint64 rl_0 = R_rl_0.read(ba);
9718  rl += rl_0;
9719  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9720  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9721  partInit.getAffectedRegisters().add(reg_name[rd],64);
9722  partInit.getAffectedRegisters().add("instructionPointer",64);
9723  partInit.code() = std::string("//lr.d\n")+
9724  "etiss_uint32 exception = 0;\n"
9725  "etiss_uint32 temp = 0;\n"
9726  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9727  #if RISCV64_Pipeline1
9728  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9729  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9730  "etiss_uint32 num_stages = 4;\n"
9731  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9732  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9733  #endif
9734  #if RISCV64_Pipeline2
9735  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9736  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9737  "etiss_uint32 num_stages = 4;\n"
9738  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9739  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9740  #endif
9741 
9742  "etiss_uint64 offs = 0;\n"
9743 
9744 "if(" + toString(rd) + " != 0)\n"
9745 "{\n"
9746  "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9747  #if RISCV64_DEBUG_CALL
9748  "printf(\"offs = %#lx\\n\",offs); \n"
9749  #endif
9750  "etiss_uint64 MEM_offs;\n"
9751  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
9752  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
9753  "etiss_int64 cast_0 = MEM_offs; \n"
9754  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9755  "{\n"
9756  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9757  "}\n"
9758  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
9759  #if RISCV64_DEBUG_CALL
9760  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9761  #endif
9762  "((RISCV64*)cpu)->RES = offs;\n"
9763  #if RISCV64_DEBUG_CALL
9764  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9765  #endif
9766 "}\n"
9767 
9768 
9769  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9770 
9771  "return exception;\n"
9772 ;
9773 return true;
9774 },
9775 0,
9776 nullptr
9777 );
9778 //-------------------------------------------------------------------------------------------------------------------
9779 static InstructionDefinition sc_w_rd_rs1_rs2(
9780  ISA32_RISCV64,
9781  "sc.w",
9782  (uint32_t)0x1800202f,
9783  (uint32_t) 0xf800707f,
9784  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9785  {
9786  etiss_uint64 aq = 0;
9787  static BitArrayRange R_aq_0 (26,26);
9788  etiss_uint64 aq_0 = R_aq_0.read(ba);
9789  aq += aq_0;
9790  etiss_uint64 rs2 = 0;
9791  static BitArrayRange R_rs2_0 (24,20);
9792  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9793  rs2 += rs2_0;
9794  etiss_uint64 rs1 = 0;
9795  static BitArrayRange R_rs1_0 (19,15);
9796  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9797  rs1 += rs1_0;
9798  etiss_uint64 rd = 0;
9799  static BitArrayRange R_rd_0 (11,7);
9800  etiss_uint64 rd_0 = R_rd_0.read(ba);
9801  rd += rd_0;
9802  etiss_uint64 rl = 0;
9803  static BitArrayRange R_rl_0 (25,25);
9804  etiss_uint64 rl_0 = R_rl_0.read(ba);
9805  rl += rl_0;
9806  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9807  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9808  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9809  partInit.getAffectedRegisters().add(reg_name[rd],64);
9810  partInit.getAffectedRegisters().add("instructionPointer",64);
9811  partInit.code() = std::string("//sc.w\n")+
9812  "etiss_uint32 exception = 0;\n"
9813  "etiss_uint32 temp = 0;\n"
9814  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9815  #if RISCV64_Pipeline1
9816  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9817  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9818  "etiss_uint32 num_stages = 4;\n"
9819  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9820  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9821  #endif
9822  #if RISCV64_Pipeline2
9823  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9824  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9825  "etiss_uint32 num_stages = 4;\n"
9826  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9827  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9828  #endif
9829 
9830  "etiss_uint64 offs = 0;\n"
9831 
9832 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9833 #if RISCV64_DEBUG_CALL
9834 "printf(\"offs = %#lx\\n\",offs); \n"
9835 #endif
9836 "if(offs == ((RISCV64*)cpu)->RES)\n"
9837 "{\n"
9838  "etiss_uint32 MEM_offs;\n"
9839  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
9840  "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
9841  "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
9842  #if RISCV64_DEBUG_CALL
9843  "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
9844  #endif
9845  "if(" + toString(rd) + " != 0)\n"
9846  "{\n"
9847  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 0;\n"
9848  #if RISCV64_DEBUG_CALL
9849  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9850  #endif
9851  "}\n"
9852 
9853  "((RISCV64*)cpu)->RES = 0;\n"
9854  #if RISCV64_DEBUG_CALL
9855  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9856  #endif
9857 "}\n"
9858 
9859 "else\n"
9860 "{\n"
9861  "if(" + toString(rd) + " != 0)\n"
9862  "{\n"
9863  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 1;\n"
9864  #if RISCV64_DEBUG_CALL
9865  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9866  #endif
9867  "}\n"
9868 
9869  "((RISCV64*)cpu)->RES = 0;\n"
9870  #if RISCV64_DEBUG_CALL
9871  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9872  #endif
9873 "}\n"
9874 
9875  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9876 
9877  "return exception;\n"
9878 ;
9879 return true;
9880 },
9881 0,
9882 nullptr
9883 );
9884 //-------------------------------------------------------------------------------------------------------------------
9885 static InstructionDefinition sc_d_rd_rs1_rs2(
9886  ISA32_RISCV64,
9887  "sc.d",
9888  (uint32_t)0x1800302f,
9889  (uint32_t) 0xf800707f,
9890  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9891  {
9892  etiss_uint64 aq = 0;
9893  static BitArrayRange R_aq_0 (26,26);
9894  etiss_uint64 aq_0 = R_aq_0.read(ba);
9895  aq += aq_0;
9896  etiss_uint64 rs2 = 0;
9897  static BitArrayRange R_rs2_0 (24,20);
9898  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9899  rs2 += rs2_0;
9900  etiss_uint64 rs1 = 0;
9901  static BitArrayRange R_rs1_0 (19,15);
9902  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9903  rs1 += rs1_0;
9904  etiss_uint64 rd = 0;
9905  static BitArrayRange R_rd_0 (11,7);
9906  etiss_uint64 rd_0 = R_rd_0.read(ba);
9907  rd += rd_0;
9908  etiss_uint64 rl = 0;
9909  static BitArrayRange R_rl_0 (25,25);
9910  etiss_uint64 rl_0 = R_rl_0.read(ba);
9911  rl += rl_0;
9912  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9913  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9914  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9915  partInit.getAffectedRegisters().add(reg_name[rd],64);
9916  partInit.getAffectedRegisters().add("instructionPointer",64);
9917  partInit.code() = std::string("//sc.d\n")+
9918  "etiss_uint32 exception = 0;\n"
9919  "etiss_uint32 temp = 0;\n"
9920  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9921  #if RISCV64_Pipeline1
9922  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9923  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9924  "etiss_uint32 num_stages = 4;\n"
9925  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9926  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9927  #endif
9928  #if RISCV64_Pipeline2
9929  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9930  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9931  "etiss_uint32 num_stages = 4;\n"
9932  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9933  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9934  #endif
9935 
9936  "etiss_uint64 offs = 0;\n"
9937 
9938 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9939 #if RISCV64_DEBUG_CALL
9940 "printf(\"offs = %#lx\\n\",offs); \n"
9941 #endif
9942 "if(offs == ((RISCV64*)cpu)->RES)\n"
9943 "{\n"
9944  "etiss_uint64 MEM_offs;\n"
9945  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
9946  "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
9947  "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
9948  #if RISCV64_DEBUG_CALL
9949  "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
9950  #endif
9951  "if(" + toString(rd) + " != 0)\n"
9952  "{\n"
9953  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 0;\n"
9954  #if RISCV64_DEBUG_CALL
9955  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9956  #endif
9957  "}\n"
9958 
9959  "((RISCV64*)cpu)->RES = 0;\n"
9960  #if RISCV64_DEBUG_CALL
9961  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9962  #endif
9963 "}\n"
9964 
9965 "else\n"
9966 "{\n"
9967  "if(" + toString(rd) + " != 0)\n"
9968  "{\n"
9969  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 1;\n"
9970  #if RISCV64_DEBUG_CALL
9971  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9972  #endif
9973  "}\n"
9974 
9975  "((RISCV64*)cpu)->RES = 0;\n"
9976  #if RISCV64_DEBUG_CALL
9977  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9978  #endif
9979 "}\n"
9980 
9981  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9982 
9983  "return exception;\n"
9984 ;
9985 return true;
9986 },
9987 0,
9988 nullptr
9989 );
9990 //-------------------------------------------------------------------------------------------------------------------
9991 static InstructionDefinition amoswap_w_rd_rs1_rs2_aqu_aq_rel_rl_(
9992  ISA32_RISCV64,
9993  "amoswap.w",
9994  (uint32_t)0x800202f,
9995  (uint32_t) 0xf800707f,
9996  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9997  {
9998  etiss_uint64 aq = 0;
9999  static BitArrayRange R_aq_0 (26,26);
10000  etiss_uint64 aq_0 = R_aq_0.read(ba);
10001  aq += aq_0;
10002  etiss_uint64 rs2 = 0;
10003  static BitArrayRange R_rs2_0 (24,20);
10004  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10005  rs2 += rs2_0;
10006  etiss_uint64 rs1 = 0;
10007  static BitArrayRange R_rs1_0 (19,15);
10008  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10009  rs1 += rs1_0;
10010  etiss_uint64 rd = 0;
10011  static BitArrayRange R_rd_0 (11,7);
10012  etiss_uint64 rd_0 = R_rd_0.read(ba);
10013  rd += rd_0;
10014  etiss_uint64 rl = 0;
10015  static BitArrayRange R_rl_0 (25,25);
10016  etiss_uint64 rl_0 = R_rl_0.read(ba);
10017  rl += rl_0;
10018  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10019  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10020  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10021  partInit.getAffectedRegisters().add(reg_name[rd],64);
10022  partInit.getAffectedRegisters().add("instructionPointer",64);
10023  partInit.code() = std::string("//amoswap.w\n")+
10024  "etiss_uint32 exception = 0;\n"
10025  "etiss_uint32 temp = 0;\n"
10026  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10027  #if RISCV64_Pipeline1
10028  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10029  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10030  "etiss_uint32 num_stages = 4;\n"
10031  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10032  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10033  #endif
10034  #if RISCV64_Pipeline2
10035  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10036  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10037  "etiss_uint32 num_stages = 4;\n"
10038  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10039  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10040  #endif
10041 
10042  "etiss_uint64 offs = 0;\n"
10043 
10044 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10045 #if RISCV64_DEBUG_CALL
10046 "printf(\"offs = %#lx\\n\",offs); \n"
10047 #endif
10048 "if(" + toString(rd) + " != 0)\n"
10049 "{\n"
10050  "etiss_uint32 MEM_offs;\n"
10051  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10052  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10053  "etiss_int32 cast_0 = MEM_offs; \n"
10054  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10055  "{\n"
10056  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10057  "}\n"
10058  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
10059  #if RISCV64_DEBUG_CALL
10060  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10061  #endif
10062 "}\n"
10063 
10064  "etiss_uint32 MEM_offs;\n"
10065 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10066 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
10067 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10068 #if RISCV64_DEBUG_CALL
10069 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10070 #endif
10071 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10072 "{\n"
10073  "((RISCV64*)cpu)->RES = 0;\n"
10074  #if RISCV64_DEBUG_CALL
10075  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10076  #endif
10077 "}\n"
10078 
10079 
10080  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10081 
10082  "return exception;\n"
10083 ;
10084 return true;
10085 },
10086 0,
10087 nullptr
10088 );
10089 //-------------------------------------------------------------------------------------------------------------------
10090 static InstructionDefinition amoswap_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10091  ISA32_RISCV64,
10092  "amoswap.d",
10093  (uint32_t)0x800302f,
10094  (uint32_t) 0xf800707f,
10095  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10096  {
10097  etiss_uint64 aq = 0;
10098  static BitArrayRange R_aq_0 (26,26);
10099  etiss_uint64 aq_0 = R_aq_0.read(ba);
10100  aq += aq_0;
10101  etiss_uint64 rs2 = 0;
10102  static BitArrayRange R_rs2_0 (24,20);
10103  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10104  rs2 += rs2_0;
10105  etiss_uint64 rs1 = 0;
10106  static BitArrayRange R_rs1_0 (19,15);
10107  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10108  rs1 += rs1_0;
10109  etiss_uint64 rd = 0;
10110  static BitArrayRange R_rd_0 (11,7);
10111  etiss_uint64 rd_0 = R_rd_0.read(ba);
10112  rd += rd_0;
10113  etiss_uint64 rl = 0;
10114  static BitArrayRange R_rl_0 (25,25);
10115  etiss_uint64 rl_0 = R_rl_0.read(ba);
10116  rl += rl_0;
10117  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10118  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10119  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10120  partInit.getAffectedRegisters().add(reg_name[rd],64);
10121  partInit.getAffectedRegisters().add("instructionPointer",64);
10122  partInit.code() = std::string("//amoswap.d\n")+
10123  "etiss_uint32 exception = 0;\n"
10124  "etiss_uint32 temp = 0;\n"
10125  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10126  #if RISCV64_Pipeline1
10127  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10128  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10129  "etiss_uint32 num_stages = 4;\n"
10130  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10131  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10132  #endif
10133  #if RISCV64_Pipeline2
10134  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10135  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10136  "etiss_uint32 num_stages = 4;\n"
10137  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10138  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10139  #endif
10140 
10141  "etiss_uint64 offs = 0;\n"
10142 
10143 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10144 #if RISCV64_DEBUG_CALL
10145 "printf(\"offs = %#lx\\n\",offs); \n"
10146 #endif
10147 "if(" + toString(rd) + " != 0)\n"
10148 "{\n"
10149  "etiss_uint64 MEM_offs;\n"
10150  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10151  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
10152  "etiss_int64 cast_0 = MEM_offs; \n"
10153  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
10154  "{\n"
10155  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
10156  "}\n"
10157  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
10158  #if RISCV64_DEBUG_CALL
10159  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10160  #endif
10161 "}\n"
10162 
10163  "etiss_uint64 MEM_offs;\n"
10164 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10165 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
10166 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
10167 #if RISCV64_DEBUG_CALL
10168 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10169 #endif
10170 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10171 "{\n"
10172  "((RISCV64*)cpu)->RES = 0;\n"
10173  #if RISCV64_DEBUG_CALL
10174  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10175  #endif
10176 "}\n"
10177 
10178 
10179  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10180 
10181  "return exception;\n"
10182 ;
10183 return true;
10184 },
10185 0,
10186 nullptr
10187 );
10188 //-------------------------------------------------------------------------------------------------------------------
10189 static InstructionDefinition amoadd_w_rd_rs1_rs2_aqu_aq_rel_rl_(
10190  ISA32_RISCV64,
10191  "amoadd.w",
10192  (uint32_t)0x202f,
10193  (uint32_t) 0xf800707f,
10194  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10195  {
10196  etiss_uint64 aq = 0;
10197  static BitArrayRange R_aq_0 (26,26);
10198  etiss_uint64 aq_0 = R_aq_0.read(ba);
10199  aq += aq_0;
10200  etiss_uint64 rs2 = 0;
10201  static BitArrayRange R_rs2_0 (24,20);
10202  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10203  rs2 += rs2_0;
10204  etiss_uint64 rs1 = 0;
10205  static BitArrayRange R_rs1_0 (19,15);
10206  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10207  rs1 += rs1_0;
10208  etiss_uint64 rd = 0;
10209  static BitArrayRange R_rd_0 (11,7);
10210  etiss_uint64 rd_0 = R_rd_0.read(ba);
10211  rd += rd_0;
10212  etiss_uint64 rl = 0;
10213  static BitArrayRange R_rl_0 (25,25);
10214  etiss_uint64 rl_0 = R_rl_0.read(ba);
10215  rl += rl_0;
10216  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10217  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10218  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10219  partInit.getAffectedRegisters().add(reg_name[rd],64);
10220  partInit.getAffectedRegisters().add("instructionPointer",64);
10221  partInit.code() = std::string("//amoadd.w\n")+
10222  "etiss_uint32 exception = 0;\n"
10223  "etiss_uint32 temp = 0;\n"
10224  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10225  #if RISCV64_Pipeline1
10226  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10227  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10228  "etiss_uint32 num_stages = 4;\n"
10229  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10230  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10231  #endif
10232  #if RISCV64_Pipeline2
10233  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10234  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10235  "etiss_uint32 num_stages = 4;\n"
10236  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10237  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10238  #endif
10239 
10240  "etiss_uint64 offs = 0;\n"
10241  "etiss_int64 res1 = 0;\n"
10242  "etiss_uint64 res2 = 0;\n"
10243 
10244 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10245 #if RISCV64_DEBUG_CALL
10246 "printf(\"offs = %#lx\\n\",offs); \n"
10247 #endif
10248  "etiss_uint32 MEM_offs;\n"
10249 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10250 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10251 "etiss_int32 cast_0 = MEM_offs; \n"
10252 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10253 "{\n"
10254  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10255 "}\n"
10256 "res1 = (etiss_int64)cast_0;\n"
10257 #if RISCV64_DEBUG_CALL
10258 "printf(\"res1 = %#lx\\n\",res1); \n"
10259 #endif
10260 "if(" + toString(rd) + " != 0)\n"
10261 "{\n"
10262  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
10263  #if RISCV64_DEBUG_CALL
10264  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10265  #endif
10266 "}\n"
10267 
10268 "res2 = res1 + *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
10269 #if RISCV64_DEBUG_CALL
10270 "printf(\"res2 = %#lx\\n\",res2); \n"
10271 #endif
10272  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10273 "MEM_offs = res2;\n"
10274 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10275 #if RISCV64_DEBUG_CALL
10276 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10277 #endif
10278 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10279 "{\n"
10280  "((RISCV64*)cpu)->RES = 0;\n"
10281  #if RISCV64_DEBUG_CALL
10282  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10283  #endif
10284 "}\n"
10285 
10286 
10287  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10288 
10289  "return exception;\n"
10290 ;
10291 return true;
10292 },
10293 0,
10294 nullptr
10295 );
10296 //-------------------------------------------------------------------------------------------------------------------
10297 static InstructionDefinition amoadd_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10298  ISA32_RISCV64,
10299  "amoadd.d",
10300  (uint32_t)0x302f,
10301  (uint32_t) 0xf800707f,
10302  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10303  {
10304  etiss_uint64 aq = 0;
10305  static BitArrayRange R_aq_0 (26,26);
10306  etiss_uint64 aq_0 = R_aq_0.read(ba);
10307  aq += aq_0;
10308  etiss_uint64 rs2 = 0;
10309  static BitArrayRange R_rs2_0 (24,20);
10310  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10311  rs2 += rs2_0;
10312  etiss_uint64 rs1 = 0;
10313  static BitArrayRange R_rs1_0 (19,15);
10314  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10315  rs1 += rs1_0;
10316  etiss_uint64 rd = 0;
10317  static BitArrayRange R_rd_0 (11,7);
10318  etiss_uint64 rd_0 = R_rd_0.read(ba);
10319  rd += rd_0;
10320  etiss_uint64 rl = 0;
10321  static BitArrayRange R_rl_0 (25,25);
10322  etiss_uint64 rl_0 = R_rl_0.read(ba);
10323  rl += rl_0;
10324  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10325  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10326  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10327  partInit.getAffectedRegisters().add(reg_name[rd],64);
10328  partInit.getAffectedRegisters().add("instructionPointer",64);
10329  partInit.code() = std::string("//amoadd.d\n")+
10330  "etiss_uint32 exception = 0;\n"
10331  "etiss_uint32 temp = 0;\n"
10332  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10333  #if RISCV64_Pipeline1
10334  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10335  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10336  "etiss_uint32 num_stages = 4;\n"
10337  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10338  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10339  #endif
10340  #if RISCV64_Pipeline2
10341  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10342  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10343  "etiss_uint32 num_stages = 4;\n"
10344  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10345  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10346  #endif
10347 
10348  "etiss_uint64 offs = 0;\n"
10349  "etiss_int64 res = 0;\n"
10350  "etiss_uint64 res2 = 0;\n"
10351 
10352 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10353 #if RISCV64_DEBUG_CALL
10354 "printf(\"offs = %#lx\\n\",offs); \n"
10355 #endif
10356  "etiss_uint64 MEM_offs;\n"
10357 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10358 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
10359 "etiss_int64 cast_0 = MEM_offs; \n"
10360 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
10361 "{\n"
10362  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
10363 "}\n"
10364 "res = (etiss_int64)cast_0;\n"
10365 #if RISCV64_DEBUG_CALL
10366 "printf(\"res = %#lx\\n\",res); \n"
10367 #endif
10368 "if(" + toString(rd) + " != 0)\n"
10369 "{\n"
10370  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
10371  #if RISCV64_DEBUG_CALL
10372  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10373  #endif
10374 "}\n"
10375 
10376 "res2 = res + *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
10377 #if RISCV64_DEBUG_CALL
10378 "printf(\"res2 = %#lx\\n\",res2); \n"
10379 #endif
10380  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10381 "MEM_offs = res2;\n"
10382 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
10383 #if RISCV64_DEBUG_CALL
10384 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10385 #endif
10386 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10387 "{\n"
10388  "((RISCV64*)cpu)->RES = 0;\n"
10389  #if RISCV64_DEBUG_CALL
10390  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10391  #endif
10392 "}\n"
10393 
10394 
10395  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10396 
10397  "return exception;\n"
10398 ;
10399 return true;
10400 },
10401 0,
10402 nullptr
10403 );
10404 //-------------------------------------------------------------------------------------------------------------------
10405 static InstructionDefinition amoxor_w_rd_rs1_rs2_aqu_aq_rel_rl_(
10406  ISA32_RISCV64,
10407  "amoxor.w",
10408  (uint32_t)0x2000202f,
10409  (uint32_t) 0xf800707f,
10410  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10411  {
10412  etiss_uint64 aq = 0;
10413  static BitArrayRange R_aq_0 (26,26);
10414  etiss_uint64 aq_0 = R_aq_0.read(ba);
10415  aq += aq_0;
10416  etiss_uint64 rs2 = 0;
10417  static BitArrayRange R_rs2_0 (24,20);
10418  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10419  rs2 += rs2_0;
10420  etiss_uint64 rs1 = 0;
10421  static BitArrayRange R_rs1_0 (19,15);
10422  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10423  rs1 += rs1_0;
10424  etiss_uint64 rd = 0;
10425  static BitArrayRange R_rd_0 (11,7);
10426  etiss_uint64 rd_0 = R_rd_0.read(ba);
10427  rd += rd_0;
10428  etiss_uint64 rl = 0;
10429  static BitArrayRange R_rl_0 (25,25);
10430  etiss_uint64 rl_0 = R_rl_0.read(ba);
10431  rl += rl_0;
10432  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10433  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10434  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10435  partInit.getAffectedRegisters().add(reg_name[rd],64);
10436  partInit.getAffectedRegisters().add("instructionPointer",64);
10437  partInit.code() = std::string("//amoxor.w\n")+
10438  "etiss_uint32 exception = 0;\n"
10439  "etiss_uint32 temp = 0;\n"
10440  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10441  #if RISCV64_Pipeline1
10442  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10443  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10444  "etiss_uint32 num_stages = 4;\n"
10445  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10446  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10447  #endif
10448  #if RISCV64_Pipeline2
10449  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10450  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10451  "etiss_uint32 num_stages = 4;\n"
10452  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10453  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10454  #endif
10455 
10456  "etiss_uint64 offs = 0;\n"
10457  "etiss_int64 res1 = 0;\n"
10458  "etiss_uint64 res2 = 0;\n"
10459 
10460 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10461 #if RISCV64_DEBUG_CALL
10462 "printf(\"offs = %#lx\\n\",offs); \n"
10463 #endif
10464  "etiss_uint32 MEM_offs;\n"
10465 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10466 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10467 "etiss_int32 cast_0 = MEM_offs; \n"
10468 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10469 "{\n"
10470  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10471 "}\n"
10472 "res1 = (etiss_int64)cast_0;\n"
10473 #if RISCV64_DEBUG_CALL
10474 "printf(\"res1 = %#lx\\n\",res1); \n"
10475 #endif
10476 "if(" + toString(rd) + " != 0)\n"
10477 "{\n"
10478  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
10479  #if RISCV64_DEBUG_CALL
10480  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10481  #endif
10482 "}\n"
10483 
10484 "res2 = (res1 ^ *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10485 #if RISCV64_DEBUG_CALL
10486 "printf(\"res2 = %#lx\\n\",res2); \n"
10487 #endif
10488  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10489 "MEM_offs = res2;\n"
10490 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10491 #if RISCV64_DEBUG_CALL
10492 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10493 #endif
10494 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10495 "{\n"
10496  "((RISCV64*)cpu)->RES = 0;\n"
10497  #if RISCV64_DEBUG_CALL
10498  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10499  #endif
10500 "}\n"
10501 
10502 
10503  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10504 
10505  "return exception;\n"
10506 ;
10507 return true;
10508 },
10509 0,
10510 nullptr
10511 );
10512 //-------------------------------------------------------------------------------------------------------------------
10513 static InstructionDefinition amoxor_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10514  ISA32_RISCV64,
10515  "amoxor.d",
10516  (uint32_t)0x2000302f,
10517  (uint32_t) 0xf800707f,
10518  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10519  {
10520  etiss_uint64 aq = 0;
10521  static BitArrayRange R_aq_0 (26,26);
10522  etiss_uint64 aq_0 = R_aq_0.read(ba);
10523  aq += aq_0;
10524  etiss_uint64 rs2 = 0;
10525  static BitArrayRange R_rs2_0 (24,20);
10526  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10527  rs2 += rs2_0;
10528  etiss_uint64 rs1 = 0;
10529  static BitArrayRange R_rs1_0 (19,15);
10530  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10531  rs1 += rs1_0;
10532  etiss_uint64 rd = 0;
10533  static BitArrayRange R_rd_0 (11,7);
10534  etiss_uint64 rd_0 = R_rd_0.read(ba);
10535  rd += rd_0;
10536  etiss_uint64 rl = 0;
10537  static BitArrayRange R_rl_0 (25,25);
10538  etiss_uint64 rl_0 = R_rl_0.read(ba);
10539  rl += rl_0;
10540  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10541  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10542  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10543  partInit.getAffectedRegisters().add(reg_name[rd],64);
10544  partInit.getAffectedRegisters().add("instructionPointer",64);
10545  partInit.code() = std::string("//amoxor.d\n")+
10546  "etiss_uint32 exception = 0;\n"
10547  "etiss_uint32 temp = 0;\n"
10548  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10549  #if RISCV64_Pipeline1
10550  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10551  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10552  "etiss_uint32 num_stages = 4;\n"
10553  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10554  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10555  #endif
10556  #if RISCV64_Pipeline2
10557  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10558  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10559  "etiss_uint32 num_stages = 4;\n"
10560  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10561  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10562  #endif
10563 
10564  "etiss_uint64 offs = 0;\n"
10565  "etiss_int64 res = 0;\n"
10566  "etiss_uint64 res2 = 0;\n"
10567 
10568 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10569 #if RISCV64_DEBUG_CALL
10570 "printf(\"offs = %#lx\\n\",offs); \n"
10571 #endif
10572  "etiss_uint64 MEM_offs;\n"
10573 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10574 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
10575 "etiss_int64 cast_0 = MEM_offs; \n"
10576 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
10577 "{\n"
10578  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
10579 "}\n"
10580 "res = (etiss_int64)cast_0;\n"
10581 #if RISCV64_DEBUG_CALL
10582 "printf(\"res = %#lx\\n\",res); \n"
10583 #endif
10584 "if(" + toString(rd) + " != 0)\n"
10585 "{\n"
10586  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
10587  #if RISCV64_DEBUG_CALL
10588  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10589  #endif
10590 "}\n"
10591 
10592 "res2 = (res ^ *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10593 #if RISCV64_DEBUG_CALL
10594 "printf(\"res2 = %#lx\\n\",res2); \n"
10595 #endif
10596  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10597 "MEM_offs = res2;\n"
10598 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
10599 #if RISCV64_DEBUG_CALL
10600 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10601 #endif
10602 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10603 "{\n"
10604  "((RISCV64*)cpu)->RES = 0;\n"
10605  #if RISCV64_DEBUG_CALL
10606  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10607  #endif
10608 "}\n"
10609 
10610 
10611  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10612 
10613  "return exception;\n"
10614 ;
10615 return true;
10616 },
10617 0,
10618 nullptr
10619 );
10620 //-------------------------------------------------------------------------------------------------------------------
10621 static InstructionDefinition amoand_w_rd_rs1_rs2_aqu_aq_rel_rl_(
10622  ISA32_RISCV64,
10623  "amoand.w",
10624  (uint32_t)0x6000202f,
10625  (uint32_t) 0xf800707f,
10626  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10627  {
10628  etiss_uint64 aq = 0;
10629  static BitArrayRange R_aq_0 (26,26);
10630  etiss_uint64 aq_0 = R_aq_0.read(ba);
10631  aq += aq_0;
10632  etiss_uint64 rs2 = 0;
10633  static BitArrayRange R_rs2_0 (24,20);
10634  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10635  rs2 += rs2_0;
10636  etiss_uint64 rs1 = 0;
10637  static BitArrayRange R_rs1_0 (19,15);
10638  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10639  rs1 += rs1_0;
10640  etiss_uint64 rd = 0;
10641  static BitArrayRange R_rd_0 (11,7);
10642  etiss_uint64 rd_0 = R_rd_0.read(ba);
10643  rd += rd_0;
10644  etiss_uint64 rl = 0;
10645  static BitArrayRange R_rl_0 (25,25);
10646  etiss_uint64 rl_0 = R_rl_0.read(ba);
10647  rl += rl_0;
10648  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10649  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10650  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10651  partInit.getAffectedRegisters().add(reg_name[rd],64);
10652  partInit.getAffectedRegisters().add("instructionPointer",64);
10653  partInit.code() = std::string("//amoand.w\n")+
10654  "etiss_uint32 exception = 0;\n"
10655  "etiss_uint32 temp = 0;\n"
10656  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10657  #if RISCV64_Pipeline1
10658  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10659  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10660  "etiss_uint32 num_stages = 4;\n"
10661  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10662  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10663  #endif
10664  #if RISCV64_Pipeline2
10665  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10666  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10667  "etiss_uint32 num_stages = 4;\n"
10668  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10669  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10670  #endif
10671 
10672  "etiss_uint64 offs = 0;\n"
10673  "etiss_int64 res1 = 0;\n"
10674  "etiss_uint64 res2 = 0;\n"
10675 
10676 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10677 #if RISCV64_DEBUG_CALL
10678 "printf(\"offs = %#lx\\n\",offs); \n"
10679 #endif
10680  "etiss_uint32 MEM_offs;\n"
10681 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10682 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10683 "etiss_int32 cast_0 = MEM_offs; \n"
10684 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10685 "{\n"
10686  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10687 "}\n"
10688 "res1 = (etiss_int64)cast_0;\n"
10689 #if RISCV64_DEBUG_CALL
10690 "printf(\"res1 = %#lx\\n\",res1); \n"
10691 #endif
10692 "if(" + toString(rd) + " != 0)\n"
10693 "{\n"
10694  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
10695  #if RISCV64_DEBUG_CALL
10696  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10697  #endif
10698 "}\n"
10699 
10700 "res2 = (res1 & *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10701 #if RISCV64_DEBUG_CALL
10702 "printf(\"res2 = %#lx\\n\",res2); \n"
10703 #endif
10704  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10705 "MEM_offs = res2;\n"
10706 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10707 #if RISCV64_DEBUG_CALL
10708 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10709 #endif
10710 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10711 "{\n"
10712  "((RISCV64*)cpu)->RES = 0;\n"
10713  #if RISCV64_DEBUG_CALL
10714  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10715  #endif
10716 "}\n"
10717 
10718 
10719  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10720 
10721  "return exception;\n"
10722 ;
10723 return true;
10724 },
10725 0,
10726 nullptr
10727 );
10728 //-------------------------------------------------------------------------------------------------------------------
10729 static InstructionDefinition amoand_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10730  ISA32_RISCV64,
10731  "amoand.d",
10732  (uint32_t)0x6000302f,
10733  (uint32_t) 0xf800707f,
10734  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10735  {
10736  etiss_uint64 aq = 0;
10737  static BitArrayRange R_aq_0 (26,26);
10738  etiss_uint64 aq_0 = R_aq_0.read(ba);
10739  aq += aq_0;
10740  etiss_uint64 rs2 = 0;
10741  static BitArrayRange R_rs2_0 (24,20);
10742  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10743  rs2 += rs2_0;
10744  etiss_uint64 rs1 = 0;
10745  static BitArrayRange R_rs1_0 (19,15);
10746  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10747  rs1 += rs1_0;
10748  etiss_uint64 rd = 0;
10749  static BitArrayRange R_rd_0 (11,7);
10750  etiss_uint64 rd_0 = R_rd_0.read(ba);
10751  rd += rd_0;
10752  etiss_uint64 rl = 0;
10753  static BitArrayRange R_rl_0 (25,25);
10754  etiss_uint64 rl_0 = R_rl_0.read(ba);
10755  rl += rl_0;
10756  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10757  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10758  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10759  partInit.getAffectedRegisters().add(reg_name[rd],64);
10760  partInit.getAffectedRegisters().add("instructionPointer",64);
10761  partInit.code() = std::string("//amoand.d\n")+
10762  "etiss_uint32 exception = 0;\n"
10763  "etiss_uint32 temp = 0;\n"
10764  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10765  #if RISCV64_Pipeline1
10766  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10767  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10768  "etiss_uint32 num_stages = 4;\n"
10769  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10770  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10771  #endif
10772  #if RISCV64_Pipeline2
10773  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10774  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10775  "etiss_uint32 num_stages = 4;\n"
10776  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10777  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10778  #endif
10779 
10780  "etiss_uint64 offs = 0;\n"
10781  "etiss_int64 res = 0;\n"
10782  "etiss_uint64 res2 = 0;\n"
10783 
10784 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10785 #if RISCV64_DEBUG_CALL
10786 "printf(\"offs = %#lx\\n\",offs); \n"
10787 #endif
10788  "etiss_uint64 MEM_offs;\n"
10789 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10790 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
10791 "etiss_int64 cast_0 = MEM_offs; \n"
10792 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
10793 "{\n"
10794  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
10795 "}\n"
10796 "res = (etiss_int64)cast_0;\n"
10797 #if RISCV64_DEBUG_CALL
10798 "printf(\"res = %#lx\\n\",res); \n"
10799 #endif
10800 "if(" + toString(rd) + " != 0)\n"
10801 "{\n"
10802  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
10803  #if RISCV64_DEBUG_CALL
10804  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10805  #endif
10806 "}\n"
10807 
10808 "res2 = (res & *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10809 #if RISCV64_DEBUG_CALL
10810 "printf(\"res2 = %#lx\\n\",res2); \n"
10811 #endif
10812  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10813 "MEM_offs = res2;\n"
10814 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
10815 #if RISCV64_DEBUG_CALL
10816 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10817 #endif
10818 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10819 "{\n"
10820  "((RISCV64*)cpu)->RES = 0;\n"
10821  #if RISCV64_DEBUG_CALL
10822  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10823  #endif
10824 "}\n"
10825 
10826 
10827  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10828 
10829  "return exception;\n"
10830 ;
10831 return true;
10832 },
10833 0,
10834 nullptr
10835 );
10836 //-------------------------------------------------------------------------------------------------------------------
10837 static InstructionDefinition amoor_w_rd_rs1_rs2_aqu_aq_rel_rl_(
10838  ISA32_RISCV64,
10839  "amoor.w",
10840  (uint32_t)0x4000202f,
10841  (uint32_t) 0xf800707f,
10842  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10843  {
10844  etiss_uint64 aq = 0;
10845  static BitArrayRange R_aq_0 (26,26);
10846  etiss_uint64 aq_0 = R_aq_0.read(ba);
10847  aq += aq_0;
10848  etiss_uint64 rs2 = 0;
10849  static BitArrayRange R_rs2_0 (24,20);
10850  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10851  rs2 += rs2_0;
10852  etiss_uint64 rs1 = 0;
10853  static BitArrayRange R_rs1_0 (19,15);
10854  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10855  rs1 += rs1_0;
10856  etiss_uint64 rd = 0;
10857  static BitArrayRange R_rd_0 (11,7);
10858  etiss_uint64 rd_0 = R_rd_0.read(ba);
10859  rd += rd_0;
10860  etiss_uint64 rl = 0;
10861  static BitArrayRange R_rl_0 (25,25);
10862  etiss_uint64 rl_0 = R_rl_0.read(ba);
10863  rl += rl_0;
10864  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10865  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10866  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10867  partInit.getAffectedRegisters().add(reg_name[rd],64);
10868  partInit.getAffectedRegisters().add("instructionPointer",64);
10869  partInit.code() = std::string("//amoor.w\n")+
10870  "etiss_uint32 exception = 0;\n"
10871  "etiss_uint32 temp = 0;\n"
10872  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10873  #if RISCV64_Pipeline1
10874  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10875  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10876  "etiss_uint32 num_stages = 4;\n"
10877  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10878  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10879  #endif
10880  #if RISCV64_Pipeline2
10881  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10882  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10883  "etiss_uint32 num_stages = 4;\n"
10884  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10885  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10886  #endif
10887 
10888  "etiss_uint64 offs = 0;\n"
10889  "etiss_int64 res1 = 0;\n"
10890  "etiss_uint64 res2 = 0;\n"
10891 
10892 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10893 #if RISCV64_DEBUG_CALL
10894 "printf(\"offs = %#lx\\n\",offs); \n"
10895 #endif
10896  "etiss_uint32 MEM_offs;\n"
10897 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10898 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10899 "etiss_int32 cast_0 = MEM_offs; \n"
10900 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10901 "{\n"
10902  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10903 "}\n"
10904 "res1 = (etiss_int64)cast_0;\n"
10905 #if RISCV64_DEBUG_CALL
10906 "printf(\"res1 = %#lx\\n\",res1); \n"
10907 #endif
10908 "if(" + toString(rd) + " != 0)\n"
10909 "{\n"
10910  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
10911  #if RISCV64_DEBUG_CALL
10912  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10913  #endif
10914 "}\n"
10915 
10916 "res2 = (res1 | *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10917 #if RISCV64_DEBUG_CALL
10918 "printf(\"res2 = %#lx\\n\",res2); \n"
10919 #endif
10920  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10921 "MEM_offs = res2;\n"
10922 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10923 #if RISCV64_DEBUG_CALL
10924 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10925 #endif
10926 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10927 "{\n"
10928  "((RISCV64*)cpu)->RES = 0;\n"
10929  #if RISCV64_DEBUG_CALL
10930  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10931  #endif
10932 "}\n"
10933 
10934 
10935  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10936 
10937  "return exception;\n"
10938 ;
10939 return true;
10940 },
10941 0,
10942 nullptr
10943 );
10944 //-------------------------------------------------------------------------------------------------------------------
10945 static InstructionDefinition amoor_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10946  ISA32_RISCV64,
10947  "amoor.d",
10948  (uint32_t)0x4000302f,
10949  (uint32_t) 0xf800707f,
10950  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10951  {
10952  etiss_uint64 aq = 0;
10953  static BitArrayRange R_aq_0 (26,26);
10954  etiss_uint64 aq_0 = R_aq_0.read(ba);
10955  aq += aq_0;
10956  etiss_uint64 rs2 = 0;
10957  static BitArrayRange R_rs2_0 (24,20);
10958  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10959  rs2 += rs2_0;
10960  etiss_uint64 rs1 = 0;
10961  static BitArrayRange R_rs1_0 (19,15);
10962  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10963  rs1 += rs1_0;
10964  etiss_uint64 rd = 0;
10965  static BitArrayRange R_rd_0 (11,7);
10966  etiss_uint64 rd_0 = R_rd_0.read(ba);
10967  rd += rd_0;
10968  etiss_uint64 rl = 0;
10969  static BitArrayRange R_rl_0 (25,25);
10970  etiss_uint64 rl_0 = R_rl_0.read(ba);
10971  rl += rl_0;
10972  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10973  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10974  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10975  partInit.getAffectedRegisters().add(reg_name[rd],64);
10976  partInit.getAffectedRegisters().add("instructionPointer",64);
10977  partInit.code() = std::string("//amoor.d\n")+
10978  "etiss_uint32 exception = 0;\n"
10979  "etiss_uint32 temp = 0;\n"
10980  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10981  #if RISCV64_Pipeline1
10982  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10983  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10984  "etiss_uint32 num_stages = 4;\n"
10985  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10986  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10987  #endif
10988  #if RISCV64_Pipeline2
10989  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10990  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10991  "etiss_uint32 num_stages = 4;\n"
10992  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10993  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10994  #endif
10995 
10996  "etiss_uint64 offs = 0;\n"
10997  "etiss_int64 res = 0;\n"
10998  "etiss_uint64 res2 = 0;\n"
10999 
11000 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11001 #if RISCV64_DEBUG_CALL
11002 "printf(\"offs = %#lx\\n\",offs); \n"
11003 #endif
11004  "etiss_uint64 MEM_offs;\n"
11005 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11006 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
11007 "etiss_int64 cast_0 = MEM_offs; \n"
11008 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
11009 "{\n"
11010  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
11011 "}\n"
11012 "res = (etiss_int64)cast_0;\n"
11013 #if RISCV64_DEBUG_CALL
11014 "printf(\"res = %#lx\\n\",res); \n"
11015 #endif
11016 "if(" + toString(rd) + " != 0)\n"
11017 "{\n"
11018  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
11019  #if RISCV64_DEBUG_CALL
11020  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11021  #endif
11022 "}\n"
11023 
11024 "res2 = (res | *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
11025 #if RISCV64_DEBUG_CALL
11026 "printf(\"res2 = %#lx\\n\",res2); \n"
11027 #endif
11028  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11029 "MEM_offs = res2;\n"
11030 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
11031 #if RISCV64_DEBUG_CALL
11032 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11033 #endif
11034 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11035 "{\n"
11036  "((RISCV64*)cpu)->RES = 0;\n"
11037  #if RISCV64_DEBUG_CALL
11038  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11039  #endif
11040 "}\n"
11041 
11042 
11043  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11044 
11045  "return exception;\n"
11046 ;
11047 return true;
11048 },
11049 0,
11050 nullptr
11051 );
11052 //-------------------------------------------------------------------------------------------------------------------
11053 static InstructionDefinition amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_(
11054  ISA32_RISCV64,
11055  "amomin.w",
11056  (uint32_t)0x8000202f,
11057  (uint32_t) 0xf800707f,
11058  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11059  {
11060  etiss_uint64 aq = 0;
11061  static BitArrayRange R_aq_0 (26,26);
11062  etiss_uint64 aq_0 = R_aq_0.read(ba);
11063  aq += aq_0;
11064  etiss_uint64 rs2 = 0;
11065  static BitArrayRange R_rs2_0 (24,20);
11066  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11067  rs2 += rs2_0;
11068  etiss_uint64 rs1 = 0;
11069  static BitArrayRange R_rs1_0 (19,15);
11070  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11071  rs1 += rs1_0;
11072  etiss_uint64 rd = 0;
11073  static BitArrayRange R_rd_0 (11,7);
11074  etiss_uint64 rd_0 = R_rd_0.read(ba);
11075  rd += rd_0;
11076  etiss_uint64 rl = 0;
11077  static BitArrayRange R_rl_0 (25,25);
11078  etiss_uint64 rl_0 = R_rl_0.read(ba);
11079  rl += rl_0;
11080  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11081  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11082  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11083  partInit.getAffectedRegisters().add(reg_name[rd],64);
11084  partInit.getAffectedRegisters().add("instructionPointer",64);
11085  partInit.code() = std::string("//amomin.w\n")+
11086  "etiss_uint32 exception = 0;\n"
11087  "etiss_uint32 temp = 0;\n"
11088  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11089  #if RISCV64_Pipeline1
11090  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11091  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11092  "etiss_uint32 num_stages = 4;\n"
11093  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11094  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11095  #endif
11096  #if RISCV64_Pipeline2
11097  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11098  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11099  "etiss_uint32 num_stages = 4;\n"
11100  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11101  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11102  #endif
11103 
11104  "etiss_uint64 offs = 0;\n"
11105  "etiss_int64 res1 = 0;\n"
11106  "etiss_uint64 res2 = 0;\n"
11107  "etiss_uint64 choose1 = 0;\n"
11108 
11109 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11110 #if RISCV64_DEBUG_CALL
11111 "printf(\"offs = %#lx\\n\",offs); \n"
11112 #endif
11113  "etiss_uint32 MEM_offs;\n"
11114 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11115 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
11116 "etiss_int32 cast_0 = MEM_offs; \n"
11117 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
11118 "{\n"
11119  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
11120 "}\n"
11121 "res1 = (etiss_int64)cast_0;\n"
11122 #if RISCV64_DEBUG_CALL
11123 "printf(\"res1 = %#lx\\n\",res1); \n"
11124 #endif
11125 "if(" + toString(rd) + " != 0)\n"
11126 "{\n"
11127  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11128  #if RISCV64_DEBUG_CALL
11129  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11130  #endif
11131 "}\n"
11132 
11133 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
11134 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
11135 "{\n"
11136  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
11137 "}\n"
11138 "etiss_int64 cast_2 = res1; \n"
11139 "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
11140 "{\n"
11141  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
11142 "}\n"
11143 "if((etiss_int64)cast_2 > (etiss_int64)cast_1)\n"
11144 "{\n"
11145  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11146  #if RISCV64_DEBUG_CALL
11147  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11148  #endif
11149 "}\n"
11150 
11151 "else\n"
11152 "{\n"
11153  "choose1 = res1;\n"
11154  #if RISCV64_DEBUG_CALL
11155  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11156  #endif
11157 "}\n"
11158 "res2 = choose1;\n"
11159 #if RISCV64_DEBUG_CALL
11160 "printf(\"res2 = %#lx\\n\",res2); \n"
11161 #endif
11162  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11163 "MEM_offs = res2;\n"
11164 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
11165 #if RISCV64_DEBUG_CALL
11166 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11167 #endif
11168 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11169 "{\n"
11170  "((RISCV64*)cpu)->RES = 0;\n"
11171  #if RISCV64_DEBUG_CALL
11172  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11173  #endif
11174 "}\n"
11175 
11176 
11177  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11178 
11179  "return exception;\n"
11180 ;
11181 return true;
11182 },
11183 0,
11184 nullptr
11185 );
11186 //-------------------------------------------------------------------------------------------------------------------
11187 static InstructionDefinition amomin_d_rd_rs1_rs2_aqu_aq_rel_rl_(
11188  ISA32_RISCV64,
11189  "amomin.d",
11190  (uint32_t)0x8000302f,
11191  (uint32_t) 0xf800707f,
11192  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11193  {
11194  etiss_uint64 aq = 0;
11195  static BitArrayRange R_aq_0 (26,26);
11196  etiss_uint64 aq_0 = R_aq_0.read(ba);
11197  aq += aq_0;
11198  etiss_uint64 rs2 = 0;
11199  static BitArrayRange R_rs2_0 (24,20);
11200  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11201  rs2 += rs2_0;
11202  etiss_uint64 rs1 = 0;
11203  static BitArrayRange R_rs1_0 (19,15);
11204  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11205  rs1 += rs1_0;
11206  etiss_uint64 rd = 0;
11207  static BitArrayRange R_rd_0 (11,7);
11208  etiss_uint64 rd_0 = R_rd_0.read(ba);
11209  rd += rd_0;
11210  etiss_uint64 rl = 0;
11211  static BitArrayRange R_rl_0 (25,25);
11212  etiss_uint64 rl_0 = R_rl_0.read(ba);
11213  rl += rl_0;
11214  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11215  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11216  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11217  partInit.getAffectedRegisters().add(reg_name[rd],64);
11218  partInit.getAffectedRegisters().add("instructionPointer",64);
11219  partInit.code() = std::string("//amomin.d\n")+
11220  "etiss_uint32 exception = 0;\n"
11221  "etiss_uint32 temp = 0;\n"
11222  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11223  #if RISCV64_Pipeline1
11224  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11225  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11226  "etiss_uint32 num_stages = 4;\n"
11227  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11228  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11229  #endif
11230  #if RISCV64_Pipeline2
11231  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11232  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11233  "etiss_uint32 num_stages = 4;\n"
11234  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11235  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11236  #endif
11237 
11238  "etiss_uint64 offs = 0;\n"
11239  "etiss_int64 res1 = 0;\n"
11240  "etiss_uint64 res2 = 0;\n"
11241  "etiss_uint64 choose1 = 0;\n"
11242 
11243 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11244 #if RISCV64_DEBUG_CALL
11245 "printf(\"offs = %#lx\\n\",offs); \n"
11246 #endif
11247  "etiss_uint64 MEM_offs;\n"
11248 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11249 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
11250 "etiss_int64 cast_0 = MEM_offs; \n"
11251 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
11252 "{\n"
11253  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
11254 "}\n"
11255 "res1 = (etiss_int64)cast_0;\n"
11256 #if RISCV64_DEBUG_CALL
11257 "printf(\"res1 = %#lx\\n\",res1); \n"
11258 #endif
11259 "if(" + toString(rd) + " != 0)\n"
11260 "{\n"
11261  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11262  #if RISCV64_DEBUG_CALL
11263  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11264  #endif
11265 "}\n"
11266 
11267 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
11268 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
11269 "{\n"
11270  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
11271 "}\n"
11272 "etiss_int64 cast_2 = res1; \n"
11273 "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
11274 "{\n"
11275  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
11276 "}\n"
11277 "if((etiss_int64)cast_2 > (etiss_int64)cast_1)\n"
11278 "{\n"
11279  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11280  #if RISCV64_DEBUG_CALL
11281  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11282  #endif
11283 "}\n"
11284 
11285 "else\n"
11286 "{\n"
11287  "choose1 = res1;\n"
11288  #if RISCV64_DEBUG_CALL
11289  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11290  #endif
11291 "}\n"
11292 "res2 = choose1;\n"
11293 #if RISCV64_DEBUG_CALL
11294 "printf(\"res2 = %#lx\\n\",res2); \n"
11295 #endif
11296  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11297 "MEM_offs = res2;\n"
11298 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
11299 #if RISCV64_DEBUG_CALL
11300 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11301 #endif
11302 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11303 "{\n"
11304  "((RISCV64*)cpu)->RES = 0;\n"
11305  #if RISCV64_DEBUG_CALL
11306  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11307  #endif
11308 "}\n"
11309 
11310 
11311  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11312 
11313  "return exception;\n"
11314 ;
11315 return true;
11316 },
11317 0,
11318 nullptr
11319 );
11320 //-------------------------------------------------------------------------------------------------------------------
11321 static InstructionDefinition amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_(
11322  ISA32_RISCV64,
11323  "amomax.w",
11324  (uint32_t)0xa000202f,
11325  (uint32_t) 0xf800707f,
11326  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11327  {
11328  etiss_uint64 aq = 0;
11329  static BitArrayRange R_aq_0 (26,26);
11330  etiss_uint64 aq_0 = R_aq_0.read(ba);
11331  aq += aq_0;
11332  etiss_uint64 rs2 = 0;
11333  static BitArrayRange R_rs2_0 (24,20);
11334  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11335  rs2 += rs2_0;
11336  etiss_uint64 rs1 = 0;
11337  static BitArrayRange R_rs1_0 (19,15);
11338  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11339  rs1 += rs1_0;
11340  etiss_uint64 rd = 0;
11341  static BitArrayRange R_rd_0 (11,7);
11342  etiss_uint64 rd_0 = R_rd_0.read(ba);
11343  rd += rd_0;
11344  etiss_uint64 rl = 0;
11345  static BitArrayRange R_rl_0 (25,25);
11346  etiss_uint64 rl_0 = R_rl_0.read(ba);
11347  rl += rl_0;
11348  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11349  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11350  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11351  partInit.getAffectedRegisters().add(reg_name[rd],64);
11352  partInit.getAffectedRegisters().add("instructionPointer",64);
11353  partInit.code() = std::string("//amomax.w\n")+
11354  "etiss_uint32 exception = 0;\n"
11355  "etiss_uint32 temp = 0;\n"
11356  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11357  #if RISCV64_Pipeline1
11358  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11359  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11360  "etiss_uint32 num_stages = 4;\n"
11361  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11362  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11363  #endif
11364  #if RISCV64_Pipeline2
11365  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11366  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11367  "etiss_uint32 num_stages = 4;\n"
11368  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11369  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11370  #endif
11371 
11372  "etiss_uint64 offs = 0;\n"
11373  "etiss_int64 res1 = 0;\n"
11374  "etiss_uint64 res2 = 0;\n"
11375  "etiss_uint64 choose1 = 0;\n"
11376 
11377 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11378 #if RISCV64_DEBUG_CALL
11379 "printf(\"offs = %#lx\\n\",offs); \n"
11380 #endif
11381  "etiss_uint32 MEM_offs;\n"
11382 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11383 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
11384 "etiss_int32 cast_0 = MEM_offs; \n"
11385 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
11386 "{\n"
11387  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
11388 "}\n"
11389 "res1 = (etiss_int64)cast_0;\n"
11390 #if RISCV64_DEBUG_CALL
11391 "printf(\"res1 = %#lx\\n\",res1); \n"
11392 #endif
11393 "if(" + toString(rd) + " != 0)\n"
11394 "{\n"
11395  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11396  #if RISCV64_DEBUG_CALL
11397  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11398  #endif
11399 "}\n"
11400 
11401 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
11402 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
11403 "{\n"
11404  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
11405 "}\n"
11406 "etiss_int64 cast_2 = res1; \n"
11407 "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
11408 "{\n"
11409  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
11410 "}\n"
11411 "if((etiss_int64)cast_2 < (etiss_int64)cast_1)\n"
11412 "{\n"
11413  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11414  #if RISCV64_DEBUG_CALL
11415  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11416  #endif
11417 "}\n"
11418 
11419 "else\n"
11420 "{\n"
11421  "choose1 = res1;\n"
11422  #if RISCV64_DEBUG_CALL
11423  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11424  #endif
11425 "}\n"
11426 "res2 = choose1;\n"
11427 #if RISCV64_DEBUG_CALL
11428 "printf(\"res2 = %#lx\\n\",res2); \n"
11429 #endif
11430  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11431 "MEM_offs = res2;\n"
11432 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
11433 #if RISCV64_DEBUG_CALL
11434 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11435 #endif
11436 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11437 "{\n"
11438  "((RISCV64*)cpu)->RES = 0;\n"
11439  #if RISCV64_DEBUG_CALL
11440  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11441  #endif
11442 "}\n"
11443 
11444 
11445  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11446 
11447  "return exception;\n"
11448 ;
11449 return true;
11450 },
11451 0,
11452 nullptr
11453 );
11454 //-------------------------------------------------------------------------------------------------------------------
11455 static InstructionDefinition amomax_d_rd_rs1_rs2_aqu_aq_rel_rl_(
11456  ISA32_RISCV64,
11457  "amomax.d",
11458  (uint32_t)0xa000302f,
11459  (uint32_t) 0xf800707f,
11460  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11461  {
11462  etiss_uint64 aq = 0;
11463  static BitArrayRange R_aq_0 (26,26);
11464  etiss_uint64 aq_0 = R_aq_0.read(ba);
11465  aq += aq_0;
11466  etiss_uint64 rs2 = 0;
11467  static BitArrayRange R_rs2_0 (24,20);
11468  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11469  rs2 += rs2_0;
11470  etiss_uint64 rs1 = 0;
11471  static BitArrayRange R_rs1_0 (19,15);
11472  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11473  rs1 += rs1_0;
11474  etiss_uint64 rd = 0;
11475  static BitArrayRange R_rd_0 (11,7);
11476  etiss_uint64 rd_0 = R_rd_0.read(ba);
11477  rd += rd_0;
11478  etiss_uint64 rl = 0;
11479  static BitArrayRange R_rl_0 (25,25);
11480  etiss_uint64 rl_0 = R_rl_0.read(ba);
11481  rl += rl_0;
11482  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11483  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11484  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11485  partInit.getAffectedRegisters().add(reg_name[rd],64);
11486  partInit.getAffectedRegisters().add("instructionPointer",64);
11487  partInit.code() = std::string("//amomax.d\n")+
11488  "etiss_uint32 exception = 0;\n"
11489  "etiss_uint32 temp = 0;\n"
11490  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11491  #if RISCV64_Pipeline1
11492  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11493  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11494  "etiss_uint32 num_stages = 4;\n"
11495  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11496  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11497  #endif
11498  #if RISCV64_Pipeline2
11499  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11500  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11501  "etiss_uint32 num_stages = 4;\n"
11502  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11503  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11504  #endif
11505 
11506  "etiss_uint64 offs = 0;\n"
11507  "etiss_int64 res = 0;\n"
11508  "etiss_uint64 res2 = 0;\n"
11509  "etiss_uint64 choose1 = 0;\n"
11510 
11511 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11512 #if RISCV64_DEBUG_CALL
11513 "printf(\"offs = %#lx\\n\",offs); \n"
11514 #endif
11515  "etiss_uint64 MEM_offs;\n"
11516 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11517 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
11518 "etiss_int64 cast_0 = MEM_offs; \n"
11519 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
11520 "{\n"
11521  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
11522 "}\n"
11523 "res = (etiss_int64)cast_0;\n"
11524 #if RISCV64_DEBUG_CALL
11525 "printf(\"res = %#lx\\n\",res); \n"
11526 #endif
11527 "if(" + toString(rd) + " != 0)\n"
11528 "{\n"
11529  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
11530  #if RISCV64_DEBUG_CALL
11531  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11532  #endif
11533 "}\n"
11534 
11535 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
11536 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
11537 "{\n"
11538  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
11539 "}\n"
11540 "etiss_int64 cast_2 = res; \n"
11541 "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
11542 "{\n"
11543  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
11544 "}\n"
11545 "if((etiss_int64)cast_2 < (etiss_int64)cast_1)\n"
11546 "{\n"
11547  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11548  #if RISCV64_DEBUG_CALL
11549  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11550  #endif
11551 "}\n"
11552 
11553 "else\n"
11554 "{\n"
11555  "choose1 = res;\n"
11556  #if RISCV64_DEBUG_CALL
11557  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11558  #endif
11559 "}\n"
11560 "res2 = choose1;\n"
11561 #if RISCV64_DEBUG_CALL
11562 "printf(\"res2 = %#lx\\n\",res2); \n"
11563 #endif
11564  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11565 "MEM_offs = res2;\n"
11566 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
11567 #if RISCV64_DEBUG_CALL
11568 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11569 #endif
11570 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11571 "{\n"
11572  "((RISCV64*)cpu)->RES = 0;\n"
11573  #if RISCV64_DEBUG_CALL
11574  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11575  #endif
11576 "}\n"
11577 
11578 
11579  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11580 
11581  "return exception;\n"
11582 ;
11583 return true;
11584 },
11585 0,
11586 nullptr
11587 );
11588 //-------------------------------------------------------------------------------------------------------------------
11589 static InstructionDefinition amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_(
11590  ISA32_RISCV64,
11591  "amominu.w",
11592  (uint32_t)0xc000202f,
11593  (uint32_t) 0xf800707f,
11594  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11595  {
11596  etiss_uint64 aq = 0;
11597  static BitArrayRange R_aq_0 (26,26);
11598  etiss_uint64 aq_0 = R_aq_0.read(ba);
11599  aq += aq_0;
11600  etiss_uint64 rs2 = 0;
11601  static BitArrayRange R_rs2_0 (24,20);
11602  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11603  rs2 += rs2_0;
11604  etiss_uint64 rs1 = 0;
11605  static BitArrayRange R_rs1_0 (19,15);
11606  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11607  rs1 += rs1_0;
11608  etiss_uint64 rd = 0;
11609  static BitArrayRange R_rd_0 (11,7);
11610  etiss_uint64 rd_0 = R_rd_0.read(ba);
11611  rd += rd_0;
11612  etiss_uint64 rl = 0;
11613  static BitArrayRange R_rl_0 (25,25);
11614  etiss_uint64 rl_0 = R_rl_0.read(ba);
11615  rl += rl_0;
11616  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11617  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11618  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11619  partInit.getAffectedRegisters().add(reg_name[rd],64);
11620  partInit.getAffectedRegisters().add("instructionPointer",64);
11621  partInit.code() = std::string("//amominu.w\n")+
11622  "etiss_uint32 exception = 0;\n"
11623  "etiss_uint32 temp = 0;\n"
11624  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11625  #if RISCV64_Pipeline1
11626  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11627  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11628  "etiss_uint32 num_stages = 4;\n"
11629  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11630  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11631  #endif
11632  #if RISCV64_Pipeline2
11633  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11634  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11635  "etiss_uint32 num_stages = 4;\n"
11636  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11637  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11638  #endif
11639 
11640  "etiss_uint64 offs = 0;\n"
11641  "etiss_int64 res1 = 0;\n"
11642  "etiss_uint64 res2 = 0;\n"
11643  "etiss_uint64 choose1 = 0;\n"
11644 
11645 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11646 #if RISCV64_DEBUG_CALL
11647 "printf(\"offs = %#lx\\n\",offs); \n"
11648 #endif
11649  "etiss_uint32 MEM_offs;\n"
11650 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11651 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
11652 "etiss_int32 cast_0 = MEM_offs; \n"
11653 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
11654 "{\n"
11655  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
11656 "}\n"
11657 "res1 = (etiss_int64)cast_0;\n"
11658 #if RISCV64_DEBUG_CALL
11659 "printf(\"res1 = %#lx\\n\",res1); \n"
11660 #endif
11661 "if(" + toString(rd) + " != 0)\n"
11662 "{\n"
11663  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11664  #if RISCV64_DEBUG_CALL
11665  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11666  #endif
11667 "}\n"
11668 
11669 "if(res1 > *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
11670 "{\n"
11671  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11672  #if RISCV64_DEBUG_CALL
11673  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11674  #endif
11675 "}\n"
11676 
11677 "else\n"
11678 "{\n"
11679  "choose1 = res1;\n"
11680  #if RISCV64_DEBUG_CALL
11681  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11682  #endif
11683 "}\n"
11684 "res2 = choose1;\n"
11685 #if RISCV64_DEBUG_CALL
11686 "printf(\"res2 = %#lx\\n\",res2); \n"
11687 #endif
11688  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11689 "MEM_offs = res2;\n"
11690 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
11691 #if RISCV64_DEBUG_CALL
11692 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11693 #endif
11694 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11695 "{\n"
11696  "((RISCV64*)cpu)->RES = 0;\n"
11697  #if RISCV64_DEBUG_CALL
11698  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11699  #endif
11700 "}\n"
11701 
11702 
11703  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11704 
11705  "return exception;\n"
11706 ;
11707 return true;
11708 },
11709 0,
11710 nullptr
11711 );
11712 //-------------------------------------------------------------------------------------------------------------------
11713 static InstructionDefinition amominu_d_rd_rs1_rs2_aqu_aq_rel_rl_(
11714  ISA32_RISCV64,
11715  "amominu.d",
11716  (uint32_t)0xc000302f,
11717  (uint32_t) 0xf800707f,
11718  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11719  {
11720  etiss_uint64 aq = 0;
11721  static BitArrayRange R_aq_0 (26,26);
11722  etiss_uint64 aq_0 = R_aq_0.read(ba);
11723  aq += aq_0;
11724  etiss_uint64 rs2 = 0;
11725  static BitArrayRange R_rs2_0 (24,20);
11726  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11727  rs2 += rs2_0;
11728  etiss_uint64 rs1 = 0;
11729  static BitArrayRange R_rs1_0 (19,15);
11730  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11731  rs1 += rs1_0;
11732  etiss_uint64 rd = 0;
11733  static BitArrayRange R_rd_0 (11,7);
11734  etiss_uint64 rd_0 = R_rd_0.read(ba);
11735  rd += rd_0;
11736  etiss_uint64 rl = 0;
11737  static BitArrayRange R_rl_0 (25,25);
11738  etiss_uint64 rl_0 = R_rl_0.read(ba);
11739  rl += rl_0;
11740  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11741  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11742  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11743  partInit.getAffectedRegisters().add(reg_name[rd],64);
11744  partInit.getAffectedRegisters().add("instructionPointer",64);
11745  partInit.code() = std::string("//amominu.d\n")+
11746  "etiss_uint32 exception = 0;\n"
11747  "etiss_uint32 temp = 0;\n"
11748  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11749  #if RISCV64_Pipeline1
11750  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11751  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11752  "etiss_uint32 num_stages = 4;\n"
11753  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11754  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11755  #endif
11756  #if RISCV64_Pipeline2
11757  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11758  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11759  "etiss_uint32 num_stages = 4;\n"
11760  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11761  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11762  #endif
11763 
11764  "etiss_uint64 offs = 0;\n"
11765  "etiss_int64 res = 0;\n"
11766  "etiss_uint64 res2 = 0;\n"
11767  "etiss_uint64 choose1 = 0;\n"
11768 
11769 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11770 #if RISCV64_DEBUG_CALL
11771 "printf(\"offs = %#lx\\n\",offs); \n"
11772 #endif
11773  "etiss_uint64 MEM_offs;\n"
11774 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11775 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
11776 "etiss_int64 cast_0 = MEM_offs; \n"
11777 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
11778 "{\n"
11779  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
11780 "}\n"
11781 "res = (etiss_int64)cast_0;\n"
11782 #if RISCV64_DEBUG_CALL
11783 "printf(\"res = %#lx\\n\",res); \n"
11784 #endif
11785 "if(" + toString(rd) + " != 0)\n"
11786 "{\n"
11787  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
11788  #if RISCV64_DEBUG_CALL
11789  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11790  #endif
11791 "}\n"
11792 
11793 "if(res > *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
11794 "{\n"
11795  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11796  #if RISCV64_DEBUG_CALL
11797  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11798  #endif
11799 "}\n"
11800 
11801 "else\n"
11802 "{\n"
11803  "choose1 = res;\n"
11804  #if RISCV64_DEBUG_CALL
11805  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11806  #endif
11807 "}\n"
11808 "res2 = choose1;\n"
11809 #if RISCV64_DEBUG_CALL
11810 "printf(\"res2 = %#lx\\n\",res2); \n"
11811 #endif
11812  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11813 "MEM_offs = res2;\n"
11814 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
11815 #if RISCV64_DEBUG_CALL
11816 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11817 #endif
11818 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11819 "{\n"
11820  "((RISCV64*)cpu)->RES = 0;\n"
11821  #if RISCV64_DEBUG_CALL
11822  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11823  #endif
11824 "}\n"
11825 
11826 
11827  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11828 
11829  "return exception;\n"
11830 ;
11831 return true;
11832 },
11833 0,
11834 nullptr
11835 );
11836 //-------------------------------------------------------------------------------------------------------------------
11837 static InstructionDefinition amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_(
11838  ISA32_RISCV64,
11839  "amomaxu.w",
11840  (uint32_t)0xe000202f,
11841  (uint32_t) 0xf800707f,
11842  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11843  {
11844  etiss_uint64 aq = 0;
11845  static BitArrayRange R_aq_0 (26,26);
11846  etiss_uint64 aq_0 = R_aq_0.read(ba);
11847  aq += aq_0;
11848  etiss_uint64 rs2 = 0;
11849  static BitArrayRange R_rs2_0 (24,20);
11850  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11851  rs2 += rs2_0;
11852  etiss_uint64 rs1 = 0;
11853  static BitArrayRange R_rs1_0 (19,15);
11854  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11855  rs1 += rs1_0;
11856  etiss_uint64 rd = 0;
11857  static BitArrayRange R_rd_0 (11,7);
11858  etiss_uint64 rd_0 = R_rd_0.read(ba);
11859  rd += rd_0;
11860  etiss_uint64 rl = 0;
11861  static BitArrayRange R_rl_0 (25,25);
11862  etiss_uint64 rl_0 = R_rl_0.read(ba);
11863  rl += rl_0;
11864  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11865  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11866  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11867  partInit.getAffectedRegisters().add(reg_name[rd],64);
11868  partInit.getAffectedRegisters().add("instructionPointer",64);
11869  partInit.code() = std::string("//amomaxu.w\n")+
11870  "etiss_uint32 exception = 0;\n"
11871  "etiss_uint32 temp = 0;\n"
11872  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11873  #if RISCV64_Pipeline1
11874  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11875  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11876  "etiss_uint32 num_stages = 4;\n"
11877  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11878  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11879  #endif
11880  #if RISCV64_Pipeline2
11881  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11882  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11883  "etiss_uint32 num_stages = 4;\n"
11884  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11885  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11886  #endif
11887 
11888  "etiss_uint64 offs = 0;\n"
11889  "etiss_int64 res1 = 0;\n"
11890  "etiss_uint64 res2 = 0;\n"
11891  "etiss_uint64 choose1 = 0;\n"
11892 
11893 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11894 #if RISCV64_DEBUG_CALL
11895 "printf(\"offs = %#lx\\n\",offs); \n"
11896 #endif
11897  "etiss_uint32 MEM_offs;\n"
11898 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11899 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
11900 "etiss_int32 cast_0 = MEM_offs; \n"
11901 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
11902 "{\n"
11903  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
11904 "}\n"
11905 "res1 = (etiss_int64)cast_0;\n"
11906 #if RISCV64_DEBUG_CALL
11907 "printf(\"res1 = %#lx\\n\",res1); \n"
11908 #endif
11909 "if(" + toString(rd) + " != 0)\n"
11910 "{\n"
11911  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11912  #if RISCV64_DEBUG_CALL
11913  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11914  #endif
11915 "}\n"
11916 
11917 "if(res1 < *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
11918 "{\n"
11919  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11920  #if RISCV64_DEBUG_CALL
11921  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11922  #endif
11923 "}\n"
11924 
11925 "else\n"
11926 "{\n"
11927  "choose1 = res1;\n"
11928  #if RISCV64_DEBUG_CALL
11929  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11930  #endif
11931 "}\n"
11932 "res2 = choose1;\n"
11933 #if RISCV64_DEBUG_CALL
11934 "printf(\"res2 = %#lx\\n\",res2); \n"
11935 #endif
11936  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11937 "MEM_offs = res2;\n"
11938 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
11939 #if RISCV64_DEBUG_CALL
11940 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11941 #endif
11942 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11943 "{\n"
11944  "((RISCV64*)cpu)->RES = 0;\n"
11945  #if RISCV64_DEBUG_CALL
11946  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11947  #endif
11948 "}\n"
11949 
11950 
11951  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11952 
11953  "return exception;\n"
11954 ;
11955 return true;
11956 },
11957 0,
11958 nullptr
11959 );
11960 //-------------------------------------------------------------------------------------------------------------------
11961 static InstructionDefinition amomaxu_d_rd_rs1_rs2_aqu_aq_rel_rl_(
11962  ISA32_RISCV64,
11963  "amomaxu.d",
11964  (uint32_t)0xe000302f,
11965  (uint32_t) 0xf800707f,
11966  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11967  {
11968  etiss_uint64 aq = 0;
11969  static BitArrayRange R_aq_0 (26,26);
11970  etiss_uint64 aq_0 = R_aq_0.read(ba);
11971  aq += aq_0;
11972  etiss_uint64 rs2 = 0;
11973  static BitArrayRange R_rs2_0 (24,20);
11974  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11975  rs2 += rs2_0;
11976  etiss_uint64 rs1 = 0;
11977  static BitArrayRange R_rs1_0 (19,15);
11978  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11979  rs1 += rs1_0;
11980  etiss_uint64 rd = 0;
11981  static BitArrayRange R_rd_0 (11,7);
11982  etiss_uint64 rd_0 = R_rd_0.read(ba);
11983  rd += rd_0;
11984  etiss_uint64 rl = 0;
11985  static BitArrayRange R_rl_0 (25,25);
11986  etiss_uint64 rl_0 = R_rl_0.read(ba);
11987  rl += rl_0;
11988  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11989  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11990  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11991  partInit.getAffectedRegisters().add(reg_name[rd],64);
11992  partInit.getAffectedRegisters().add("instructionPointer",64);
11993  partInit.code() = std::string("//amomaxu.d\n")+
11994  "etiss_uint32 exception = 0;\n"
11995  "etiss_uint32 temp = 0;\n"
11996  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11997  #if RISCV64_Pipeline1
11998  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11999  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12000  "etiss_uint32 num_stages = 4;\n"
12001  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12002  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12003  #endif
12004  #if RISCV64_Pipeline2
12005  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12006  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12007  "etiss_uint32 num_stages = 4;\n"
12008  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12009  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12010  #endif
12011 
12012  "etiss_uint64 offs = 0;\n"
12013  "etiss_int64 res1 = 0;\n"
12014  "etiss_uint64 res2 = 0;\n"
12015  "etiss_uint64 choose1 = 0;\n"
12016 
12017 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
12018 #if RISCV64_DEBUG_CALL
12019 "printf(\"offs = %#lx\\n\",offs); \n"
12020 #endif
12021  "etiss_uint64 MEM_offs;\n"
12022 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
12023 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
12024 "etiss_int64 cast_0 = MEM_offs; \n"
12025 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
12026 "{\n"
12027  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
12028 "}\n"
12029 "res1 = (etiss_int64)cast_0;\n"
12030 #if RISCV64_DEBUG_CALL
12031 "printf(\"res1 = %#lx\\n\",res1); \n"
12032 #endif
12033 "if(" + toString(rd) + " != 0)\n"
12034 "{\n"
12035  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
12036  #if RISCV64_DEBUG_CALL
12037  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
12038  #endif
12039 "}\n"
12040 
12041 "if(res1 < *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
12042 "{\n"
12043  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
12044  #if RISCV64_DEBUG_CALL
12045  "printf(\"choose1 = %#lx\\n\",choose1); \n"
12046  #endif
12047 "}\n"
12048 
12049 "else\n"
12050 "{\n"
12051  "choose1 = res1;\n"
12052  #if RISCV64_DEBUG_CALL
12053  "printf(\"choose1 = %#lx\\n\",choose1); \n"
12054  #endif
12055 "}\n"
12056 "res2 = choose1;\n"
12057 #if RISCV64_DEBUG_CALL
12058 "printf(\"res2 = %#lx\\n\",res2); \n"
12059 #endif
12060  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
12061 "MEM_offs = res2;\n"
12062 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
12063 #if RISCV64_DEBUG_CALL
12064 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
12065 #endif
12066 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
12067 "{\n"
12068  "((RISCV64*)cpu)->RES = 0;\n"
12069  #if RISCV64_DEBUG_CALL
12070  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
12071  #endif
12072 "}\n"
12073 
12074 
12075  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12076 
12077  "return exception;\n"
12078 ;
12079 return true;
12080 },
12081 0,
12082 nullptr
12083 );
12084 //-------------------------------------------------------------------------------------------------------------------
12085 static InstructionDefinition fsub_s_rd_frs1_frs2(
12086  ISA32_RISCV64,
12087  "fsub.s",
12088  (uint32_t)0x8000053,
12089  (uint32_t) 0xfe00007f,
12090  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12091  {
12092  etiss_uint64 rs2 = 0;
12093  static BitArrayRange R_rs2_0 (24,20);
12094  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12095  rs2 += rs2_0;
12096  etiss_uint64 rs1 = 0;
12097  static BitArrayRange R_rs1_0 (19,15);
12098  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12099  rs1 += rs1_0;
12100  etiss_uint64 rd = 0;
12101  static BitArrayRange R_rd_0 (11,7);
12102  etiss_uint64 rd_0 = R_rd_0.read(ba);
12103  rd += rd_0;
12104  etiss_uint64 rm = 0;
12105  static BitArrayRange R_rm_0 (14,12);
12106  etiss_uint64 rm_0 = R_rm_0.read(ba);
12107  rm += rm_0;
12108  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12109  partInit.getAffectedRegisters().add(reg_name[rd],64);
12110  partInit.getAffectedRegisters().add("instructionPointer",64);
12111  partInit.code() = std::string("//fsub.s\n")+
12112  "etiss_uint32 temp = 0;\n"
12113  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12114  #if RISCV64_Pipeline1
12115  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12116  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12117  "etiss_uint32 num_stages = 4;\n"
12118  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12119  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12120  #endif
12121  #if RISCV64_Pipeline2
12122  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12123  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12124  "etiss_uint32 num_stages = 4;\n"
12125  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12126  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12127  #endif
12128 
12129  "etiss_uint32 res = 0;\n"
12130  "etiss_int64 upper = 0;\n"
12131  "etiss_uint32 flags = 0;\n"
12132  "etiss_uint32 frs1 = 0;\n"
12133  "etiss_uint32 choose1 = 0;\n"
12134  "etiss_uint32 frs2 = 0;\n"
12135 
12136 "if(64 == 32)\n"
12137 "{\n"
12138  "if(" + toString(rm) + " < 7)\n"
12139  "{\n"
12140  "choose1 = (" + toString(rm) + " & 0xff);\n"
12141  #if RISCV64_DEBUG_CALL
12142  "printf(\"choose1 = %#x\\n\",choose1); \n"
12143  #endif
12144  "}\n"
12145 
12146  "else\n"
12147  "{\n"
12148  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12149  #if RISCV64_DEBUG_CALL
12150  "printf(\"choose1 = %#x\\n\",choose1); \n"
12151  #endif
12152  "}\n"
12153  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fsub_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], choose1);\n"
12154  #if RISCV64_DEBUG_CALL
12155  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12156  #endif
12157 "}\n"
12158 
12159 "else\n"
12160 "{\n"
12161  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12162  #if RISCV64_DEBUG_CALL
12163  "printf(\"frs1 = %#x\\n\",frs1); \n"
12164  #endif
12165  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12166  #if RISCV64_DEBUG_CALL
12167  "printf(\"frs2 = %#x\\n\",frs2); \n"
12168  #endif
12169  "if(" + toString(rm) + " < 7)\n"
12170  "{\n"
12171  "choose1 = (" + toString(rm) + " & 0xff);\n"
12172  #if RISCV64_DEBUG_CALL
12173  "printf(\"choose1 = %#x\\n\",choose1); \n"
12174  #endif
12175  "}\n"
12176 
12177  "else\n"
12178  "{\n"
12179  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12180  #if RISCV64_DEBUG_CALL
12181  "printf(\"choose1 = %#x\\n\",choose1); \n"
12182  #endif
12183  "}\n"
12184  "res = fsub_s(frs1, frs2, choose1);\n"
12185  #if RISCV64_DEBUG_CALL
12186  "printf(\"res = %#x\\n\",res); \n"
12187  #endif
12188  "upper = - 1;\n"
12189  #if RISCV64_DEBUG_CALL
12190  "printf(\"upper = %#lx\\n\",upper); \n"
12191  #endif
12192  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12193  #if RISCV64_DEBUG_CALL
12194  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12195  #endif
12196 "}\n"
12197 "flags = fget_flags();\n"
12198 #if RISCV64_DEBUG_CALL
12199 "printf(\"flags = %#x\\n\",flags); \n"
12200 #endif
12201 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12202 #if RISCV64_DEBUG_CALL
12203 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12204 #endif
12205 
12206  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12207 
12208 ;
12209 return true;
12210 },
12211 0,
12212 nullptr
12213 );
12214 //-------------------------------------------------------------------------------------------------------------------
12215 static InstructionDefinition fdiv_s_rd_frs1_frs2(
12216  ISA32_RISCV64,
12217  "fdiv.s",
12218  (uint32_t)0x18000053,
12219  (uint32_t) 0xfe00007f,
12220  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12221  {
12222  etiss_uint64 rs2 = 0;
12223  static BitArrayRange R_rs2_0 (24,20);
12224  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12225  rs2 += rs2_0;
12226  etiss_uint64 rs1 = 0;
12227  static BitArrayRange R_rs1_0 (19,15);
12228  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12229  rs1 += rs1_0;
12230  etiss_uint64 rd = 0;
12231  static BitArrayRange R_rd_0 (11,7);
12232  etiss_uint64 rd_0 = R_rd_0.read(ba);
12233  rd += rd_0;
12234  etiss_uint64 rm = 0;
12235  static BitArrayRange R_rm_0 (14,12);
12236  etiss_uint64 rm_0 = R_rm_0.read(ba);
12237  rm += rm_0;
12238  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12239  partInit.getAffectedRegisters().add(reg_name[rd],64);
12240  partInit.getAffectedRegisters().add("instructionPointer",64);
12241  partInit.code() = std::string("//fdiv.s\n")+
12242  "etiss_uint32 temp = 0;\n"
12243  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12244  #if RISCV64_Pipeline1
12245  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12246  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12247  "etiss_uint32 num_stages = 4;\n"
12248  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12249  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12250  #endif
12251  #if RISCV64_Pipeline2
12252  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12253  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12254  "etiss_uint32 num_stages = 4;\n"
12255  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12256  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12257  #endif
12258 
12259  "etiss_uint32 res = 0;\n"
12260  "etiss_int64 upper = 0;\n"
12261  "etiss_uint32 flags = 0;\n"
12262  "etiss_uint32 frs1 = 0;\n"
12263  "etiss_uint32 choose1 = 0;\n"
12264  "etiss_uint32 frs2 = 0;\n"
12265 
12266 "if(64 == 32)\n"
12267 "{\n"
12268  "if(" + toString(rm) + " < 7)\n"
12269  "{\n"
12270  "choose1 = (" + toString(rm) + " & 0xff);\n"
12271  #if RISCV64_DEBUG_CALL
12272  "printf(\"choose1 = %#x\\n\",choose1); \n"
12273  #endif
12274  "}\n"
12275 
12276  "else\n"
12277  "{\n"
12278  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12279  #if RISCV64_DEBUG_CALL
12280  "printf(\"choose1 = %#x\\n\",choose1); \n"
12281  #endif
12282  "}\n"
12283  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fdiv_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], choose1);\n"
12284  #if RISCV64_DEBUG_CALL
12285  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12286  #endif
12287 "}\n"
12288 
12289 "else\n"
12290 "{\n"
12291  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12292  #if RISCV64_DEBUG_CALL
12293  "printf(\"frs1 = %#x\\n\",frs1); \n"
12294  #endif
12295  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12296  #if RISCV64_DEBUG_CALL
12297  "printf(\"frs2 = %#x\\n\",frs2); \n"
12298  #endif
12299  "if(" + toString(rm) + " < 7)\n"
12300  "{\n"
12301  "choose1 = (" + toString(rm) + " & 0xff);\n"
12302  #if RISCV64_DEBUG_CALL
12303  "printf(\"choose1 = %#x\\n\",choose1); \n"
12304  #endif
12305  "}\n"
12306 
12307  "else\n"
12308  "{\n"
12309  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12310  #if RISCV64_DEBUG_CALL
12311  "printf(\"choose1 = %#x\\n\",choose1); \n"
12312  #endif
12313  "}\n"
12314  "res = fdiv_s(frs1, frs2, choose1);\n"
12315  #if RISCV64_DEBUG_CALL
12316  "printf(\"res = %#x\\n\",res); \n"
12317  #endif
12318  "upper = - 1;\n"
12319  #if RISCV64_DEBUG_CALL
12320  "printf(\"upper = %#lx\\n\",upper); \n"
12321  #endif
12322  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12323  #if RISCV64_DEBUG_CALL
12324  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12325  #endif
12326 "}\n"
12327 "flags = fget_flags();\n"
12328 #if RISCV64_DEBUG_CALL
12329 "printf(\"flags = %#x\\n\",flags); \n"
12330 #endif
12331 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12332 #if RISCV64_DEBUG_CALL
12333 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12334 #endif
12335 
12336  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12337 
12338 ;
12339 return true;
12340 },
12341 0,
12342 nullptr
12343 );
12344 //-------------------------------------------------------------------------------------------------------------------
12345 static InstructionDefinition fsqrt_s_rd_frs1(
12346  ISA32_RISCV64,
12347  "fsqrt.s",
12348  (uint32_t)0x58000053,
12349  (uint32_t) 0xfff0007f,
12350  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12351  {
12352  etiss_uint64 rs1 = 0;
12353  static BitArrayRange R_rs1_0 (19,15);
12354  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12355  rs1 += rs1_0;
12356  etiss_uint64 rd = 0;
12357  static BitArrayRange R_rd_0 (11,7);
12358  etiss_uint64 rd_0 = R_rd_0.read(ba);
12359  rd += rd_0;
12360  etiss_uint64 rm = 0;
12361  static BitArrayRange R_rm_0 (14,12);
12362  etiss_uint64 rm_0 = R_rm_0.read(ba);
12363  rm += rm_0;
12364  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12365  partInit.getAffectedRegisters().add(reg_name[rd],64);
12366  partInit.getAffectedRegisters().add("instructionPointer",64);
12367  partInit.code() = std::string("//fsqrt.s\n")+
12368  "etiss_uint32 temp = 0;\n"
12369  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12370  #if RISCV64_Pipeline1
12371  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12372  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12373  "etiss_uint32 num_stages = 4;\n"
12374  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12375  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12376  #endif
12377  #if RISCV64_Pipeline2
12378  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12379  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12380  "etiss_uint32 num_stages = 4;\n"
12381  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12382  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12383  #endif
12384 
12385  "etiss_uint32 res = 0;\n"
12386  "etiss_int64 upper = 0;\n"
12387  "etiss_uint32 flags = 0;\n"
12388  "etiss_uint32 frs1 = 0;\n"
12389  "etiss_uint32 choose1 = 0;\n"
12390 
12391 "if(64 == 32)\n"
12392 "{\n"
12393  "if(" + toString(rm) + " < 7)\n"
12394  "{\n"
12395  "choose1 = (" + toString(rm) + " & 0xff);\n"
12396  #if RISCV64_DEBUG_CALL
12397  "printf(\"choose1 = %#x\\n\",choose1); \n"
12398  #endif
12399  "}\n"
12400 
12401  "else\n"
12402  "{\n"
12403  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12404  #if RISCV64_DEBUG_CALL
12405  "printf(\"choose1 = %#x\\n\",choose1); \n"
12406  #endif
12407  "}\n"
12408  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fsqrt_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], choose1);\n"
12409  #if RISCV64_DEBUG_CALL
12410  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12411  #endif
12412 "}\n"
12413 
12414 "else\n"
12415 "{\n"
12416  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12417  #if RISCV64_DEBUG_CALL
12418  "printf(\"frs1 = %#x\\n\",frs1); \n"
12419  #endif
12420  "if(" + toString(rm) + " < 7)\n"
12421  "{\n"
12422  "choose1 = (" + toString(rm) + " & 0xff);\n"
12423  #if RISCV64_DEBUG_CALL
12424  "printf(\"choose1 = %#x\\n\",choose1); \n"
12425  #endif
12426  "}\n"
12427 
12428  "else\n"
12429  "{\n"
12430  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12431  #if RISCV64_DEBUG_CALL
12432  "printf(\"choose1 = %#x\\n\",choose1); \n"
12433  #endif
12434  "}\n"
12435  "res = fsqrt_s(frs1, choose1);\n"
12436  #if RISCV64_DEBUG_CALL
12437  "printf(\"res = %#x\\n\",res); \n"
12438  #endif
12439  "upper = - 1;\n"
12440  #if RISCV64_DEBUG_CALL
12441  "printf(\"upper = %#lx\\n\",upper); \n"
12442  #endif
12443  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12444  #if RISCV64_DEBUG_CALL
12445  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12446  #endif
12447 "}\n"
12448 "flags = fget_flags();\n"
12449 #if RISCV64_DEBUG_CALL
12450 "printf(\"flags = %#x\\n\",flags); \n"
12451 #endif
12452 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12453 #if RISCV64_DEBUG_CALL
12454 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12455 #endif
12456 
12457  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12458 
12459 ;
12460 return true;
12461 },
12462 0,
12463 nullptr
12464 );
12465 //-------------------------------------------------------------------------------------------------------------------
12466 static InstructionDefinition fsgnj_s_rd_frs1_frs2(
12467  ISA32_RISCV64,
12468  "fsgnj.s",
12469  (uint32_t)0x20000053,
12470  (uint32_t) 0xfe00707f,
12471  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12472  {
12473  etiss_uint64 rs2 = 0;
12474  static BitArrayRange R_rs2_0 (24,20);
12475  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12476  rs2 += rs2_0;
12477  etiss_uint64 rs1 = 0;
12478  static BitArrayRange R_rs1_0 (19,15);
12479  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12480  rs1 += rs1_0;
12481  etiss_uint64 rd = 0;
12482  static BitArrayRange R_rd_0 (11,7);
12483  etiss_uint64 rd_0 = R_rd_0.read(ba);
12484  rd += rd_0;
12485  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12486  partInit.getRegisterDependencies().add(reg_name[rs2],64);
12487  partInit.getRegisterDependencies().add(reg_name[rs1],64);
12488  partInit.getAffectedRegisters().add(reg_name[rd],64);
12489  partInit.getAffectedRegisters().add("instructionPointer",64);
12490  partInit.code() = std::string("//fsgnj.s\n")+
12491  "etiss_uint32 temp = 0;\n"
12492  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12493  #if RISCV64_Pipeline1
12494  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12495  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12496  "etiss_uint32 num_stages = 4;\n"
12497  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12498  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12499  #endif
12500  #if RISCV64_Pipeline2
12501  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12502  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12503  "etiss_uint32 num_stages = 4;\n"
12504  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12505  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12506  #endif
12507 
12508  "etiss_uint32 res = 0;\n"
12509  "etiss_int64 upper = 0;\n"
12510  "etiss_uint32 frs1 = 0;\n"
12511  "etiss_uint32 frs2 = 0;\n"
12512 
12513 "if(64 == 32)\n"
12514 "{\n"
12515  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 2147483647) | (((RISCV64*)cpu)->F[" + toString(rs2) + "] & -2147483648));\n"
12516  #if RISCV64_DEBUG_CALL
12517  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12518  #endif
12519 "}\n"
12520 
12521 "else\n"
12522 "{\n"
12523  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12524  #if RISCV64_DEBUG_CALL
12525  "printf(\"frs1 = %#x\\n\",frs1); \n"
12526  #endif
12527  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12528  #if RISCV64_DEBUG_CALL
12529  "printf(\"frs2 = %#x\\n\",frs2); \n"
12530  #endif
12531  "res = ((frs1 & 2147483647) | (frs2 & -2147483648));\n"
12532  #if RISCV64_DEBUG_CALL
12533  "printf(\"res = %#x\\n\",res); \n"
12534  #endif
12535  "upper = - 1;\n"
12536  #if RISCV64_DEBUG_CALL
12537  "printf(\"upper = %#lx\\n\",upper); \n"
12538  #endif
12539  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12540  #if RISCV64_DEBUG_CALL
12541  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12542  #endif
12543 "}\n"
12544 
12545  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12546 
12547 ;
12548 return true;
12549 },
12550 0,
12551 nullptr
12552 );
12553 //-------------------------------------------------------------------------------------------------------------------
12554 static InstructionDefinition fsgnjn_s_rd_frs1_frs2(
12555  ISA32_RISCV64,
12556  "fsgnjn.s",
12557  (uint32_t)0x20001053,
12558  (uint32_t) 0xfe00707f,
12559  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12560  {
12561  etiss_uint64 rs2 = 0;
12562  static BitArrayRange R_rs2_0 (24,20);
12563  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12564  rs2 += rs2_0;
12565  etiss_uint64 rs1 = 0;
12566  static BitArrayRange R_rs1_0 (19,15);
12567  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12568  rs1 += rs1_0;
12569  etiss_uint64 rd = 0;
12570  static BitArrayRange R_rd_0 (11,7);
12571  etiss_uint64 rd_0 = R_rd_0.read(ba);
12572  rd += rd_0;
12573  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12574  partInit.getRegisterDependencies().add(reg_name[rs2],64);
12575  partInit.getRegisterDependencies().add(reg_name[rs1],64);
12576  partInit.getAffectedRegisters().add(reg_name[rd],64);
12577  partInit.getAffectedRegisters().add("instructionPointer",64);
12578  partInit.code() = std::string("//fsgnjn.s\n")+
12579  "etiss_uint32 temp = 0;\n"
12580  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12581  #if RISCV64_Pipeline1
12582  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12583  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12584  "etiss_uint32 num_stages = 4;\n"
12585  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12586  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12587  #endif
12588  #if RISCV64_Pipeline2
12589  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12590  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12591  "etiss_uint32 num_stages = 4;\n"
12592  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12593  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12594  #endif
12595 
12596  "etiss_uint32 res = 0;\n"
12597  "etiss_int64 upper = 0;\n"
12598  "etiss_uint32 frs1 = 0;\n"
12599  "etiss_uint32 frs2 = 0;\n"
12600 
12601 "if(64 == 32)\n"
12602 "{\n"
12603  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 2147483647) | (~((RISCV64*)cpu)->F[" + toString(rs2) + "] & -2147483648))&0xffffffffffffffff;\n"
12604  #if RISCV64_DEBUG_CALL
12605  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12606  #endif
12607 "}\n"
12608 
12609 "else\n"
12610 "{\n"
12611  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12612  #if RISCV64_DEBUG_CALL
12613  "printf(\"frs1 = %#x\\n\",frs1); \n"
12614  #endif
12615  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12616  #if RISCV64_DEBUG_CALL
12617  "printf(\"frs2 = %#x\\n\",frs2); \n"
12618  #endif
12619  "res = ((frs1 & 2147483647) | (~frs2 & -2147483648))&0xffffffff;\n"
12620  #if RISCV64_DEBUG_CALL
12621  "printf(\"res = %#x\\n\",res); \n"
12622  #endif
12623  "upper = - 1;\n"
12624  #if RISCV64_DEBUG_CALL
12625  "printf(\"upper = %#lx\\n\",upper); \n"
12626  #endif
12627  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12628  #if RISCV64_DEBUG_CALL
12629  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12630  #endif
12631 "}\n"
12632 
12633  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12634 
12635 ;
12636 return true;
12637 },
12638 0,
12639 nullptr
12640 );
12641 //-------------------------------------------------------------------------------------------------------------------
12642 static InstructionDefinition fsgnjx_s_rd_frs1_frs2(
12643  ISA32_RISCV64,
12644  "fsgnjx.s",
12645  (uint32_t)0x20002053,
12646  (uint32_t) 0xfe00707f,
12647  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12648  {
12649  etiss_uint64 rs2 = 0;
12650  static BitArrayRange R_rs2_0 (24,20);
12651  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12652  rs2 += rs2_0;
12653  etiss_uint64 rs1 = 0;
12654  static BitArrayRange R_rs1_0 (19,15);
12655  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12656  rs1 += rs1_0;
12657  etiss_uint64 rd = 0;
12658  static BitArrayRange R_rd_0 (11,7);
12659  etiss_uint64 rd_0 = R_rd_0.read(ba);
12660  rd += rd_0;
12661  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12662  partInit.getRegisterDependencies().add(reg_name[rs2],64);
12663  partInit.getRegisterDependencies().add(reg_name[rs1],64);
12664  partInit.getAffectedRegisters().add(reg_name[rd],64);
12665  partInit.getAffectedRegisters().add("instructionPointer",64);
12666  partInit.code() = std::string("//fsgnjx.s\n")+
12667  "etiss_uint32 temp = 0;\n"
12668  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12669  #if RISCV64_Pipeline1
12670  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12671  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12672  "etiss_uint32 num_stages = 4;\n"
12673  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12674  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12675  #endif
12676  #if RISCV64_Pipeline2
12677  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12678  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12679  "etiss_uint32 num_stages = 4;\n"
12680  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12681  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12682  #endif
12683 
12684  "etiss_uint32 res = 0;\n"
12685  "etiss_int64 upper = 0;\n"
12686  "etiss_uint32 frs1 = 0;\n"
12687  "etiss_uint32 frs2 = 0;\n"
12688 
12689 "if(64 == 32)\n"
12690 "{\n"
12691  "((RISCV64*)cpu)->F[" + toString(rd) + "] = (((RISCV64*)cpu)->F[" + toString(rs1) + "] ^ (((RISCV64*)cpu)->F[" + toString(rs2) + "] & -2147483648));\n"
12692  #if RISCV64_DEBUG_CALL
12693  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12694  #endif
12695 "}\n"
12696 
12697 "else\n"
12698 "{\n"
12699  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12700  #if RISCV64_DEBUG_CALL
12701  "printf(\"frs1 = %#x\\n\",frs1); \n"
12702  #endif
12703  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12704  #if RISCV64_DEBUG_CALL
12705  "printf(\"frs2 = %#x\\n\",frs2); \n"
12706  #endif
12707  "res = (frs1 ^ (frs2 & -2147483648));\n"
12708  #if RISCV64_DEBUG_CALL
12709  "printf(\"res = %#x\\n\",res); \n"
12710  #endif
12711  "upper = - 1;\n"
12712  #if RISCV64_DEBUG_CALL
12713  "printf(\"upper = %#lx\\n\",upper); \n"
12714  #endif
12715  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12716  #if RISCV64_DEBUG_CALL
12717  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12718  #endif
12719 "}\n"
12720 
12721  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12722 
12723 ;
12724 return true;
12725 },
12726 0,
12727 nullptr
12728 );
12729 //-------------------------------------------------------------------------------------------------------------------
12730 static InstructionDefinition fmin_s_rd_frs1_frs2(
12731  ISA32_RISCV64,
12732  "fmin.s",
12733  (uint32_t)0x28000053,
12734  (uint32_t) 0xfe00707f,
12735  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12736  {
12737  etiss_uint64 rs2 = 0;
12738  static BitArrayRange R_rs2_0 (24,20);
12739  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12740  rs2 += rs2_0;
12741  etiss_uint64 rs1 = 0;
12742  static BitArrayRange R_rs1_0 (19,15);
12743  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12744  rs1 += rs1_0;
12745  etiss_uint64 rd = 0;
12746  static BitArrayRange R_rd_0 (11,7);
12747  etiss_uint64 rd_0 = R_rd_0.read(ba);
12748  rd += rd_0;
12749  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12750  partInit.getAffectedRegisters().add(reg_name[rd],64);
12751  partInit.getAffectedRegisters().add("instructionPointer",64);
12752  partInit.code() = std::string("//fmin.s\n")+
12753  "etiss_uint32 temp = 0;\n"
12754  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12755  #if RISCV64_Pipeline1
12756  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12757  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12758  "etiss_uint32 num_stages = 4;\n"
12759  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12760  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12761  #endif
12762  #if RISCV64_Pipeline2
12763  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12764  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12765  "etiss_uint32 num_stages = 4;\n"
12766  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12767  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12768  #endif
12769 
12770  "etiss_uint32 res = 0;\n"
12771  "etiss_int64 upper = 0;\n"
12772  "etiss_uint32 flags = 0;\n"
12773  "etiss_uint32 frs1 = 0;\n"
12774  "etiss_uint32 frs2 = 0;\n"
12775 
12776 "if(64 == 32)\n"
12777 "{\n"
12778  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fsel_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)0);\n"
12779  #if RISCV64_DEBUG_CALL
12780  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12781  #endif
12782 "}\n"
12783 
12784 "else\n"
12785 "{\n"
12786  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12787  #if RISCV64_DEBUG_CALL
12788  "printf(\"frs1 = %#x\\n\",frs1); \n"
12789  #endif
12790  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12791  #if RISCV64_DEBUG_CALL
12792  "printf(\"frs2 = %#x\\n\",frs2); \n"
12793  #endif
12794  "res = fsel_s(frs1, frs2, (etiss_uint32)0);\n"
12795  #if RISCV64_DEBUG_CALL
12796  "printf(\"res = %#x\\n\",res); \n"
12797  #endif
12798  "upper = - 1;\n"
12799  #if RISCV64_DEBUG_CALL
12800  "printf(\"upper = %#lx\\n\",upper); \n"
12801  #endif
12802  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12803  #if RISCV64_DEBUG_CALL
12804  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12805  #endif
12806 "}\n"
12807 "flags = fget_flags();\n"
12808 #if RISCV64_DEBUG_CALL
12809 "printf(\"flags = %#x\\n\",flags); \n"
12810 #endif
12811 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12812 #if RISCV64_DEBUG_CALL
12813 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12814 #endif
12815 
12816  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12817 
12818 ;
12819 return true;
12820 },
12821 0,
12822 nullptr
12823 );
12824 //-------------------------------------------------------------------------------------------------------------------
12825 static InstructionDefinition fmax_s_rd_frs1_frs2(
12826  ISA32_RISCV64,
12827  "fmax.s",
12828  (uint32_t)0x28001053,
12829  (uint32_t) 0xfe00707f,
12830  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12831  {
12832  etiss_uint64 rs2 = 0;
12833  static BitArrayRange R_rs2_0 (24,20);
12834  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12835  rs2 += rs2_0;
12836  etiss_uint64 rs1 = 0;
12837  static BitArrayRange R_rs1_0 (19,15);
12838  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12839  rs1 += rs1_0;
12840  etiss_uint64 rd = 0;
12841  static BitArrayRange R_rd_0 (11,7);
12842  etiss_uint64 rd_0 = R_rd_0.read(ba);
12843  rd += rd_0;
12844  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12845  partInit.getAffectedRegisters().add(reg_name[rd],64);
12846  partInit.getAffectedRegisters().add("instructionPointer",64);
12847  partInit.code() = std::string("//fmax.s\n")+
12848  "etiss_uint32 temp = 0;\n"
12849  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12850  #if RISCV64_Pipeline1
12851  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12852  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12853  "etiss_uint32 num_stages = 4;\n"
12854  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12855  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12856  #endif
12857  #if RISCV64_Pipeline2
12858  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12859  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12860  "etiss_uint32 num_stages = 4;\n"
12861  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12862  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12863  #endif
12864 
12865  "etiss_uint32 res = 0;\n"
12866  "etiss_int64 upper = 0;\n"
12867  "etiss_uint32 flags = 0;\n"
12868  "etiss_uint32 frs1 = 0;\n"
12869  "etiss_uint32 frs2 = 0;\n"
12870 
12871 "if(64 == 32)\n"
12872 "{\n"
12873  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fsel_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)1);\n"
12874  #if RISCV64_DEBUG_CALL
12875  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12876  #endif
12877 "}\n"
12878 
12879 "else\n"
12880 "{\n"
12881  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12882  #if RISCV64_DEBUG_CALL
12883  "printf(\"frs1 = %#x\\n\",frs1); \n"
12884  #endif
12885  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12886  #if RISCV64_DEBUG_CALL
12887  "printf(\"frs2 = %#x\\n\",frs2); \n"
12888  #endif
12889  "res = fsel_s(frs1, frs2, (etiss_uint32)1);\n"
12890  #if RISCV64_DEBUG_CALL
12891  "printf(\"res = %#x\\n\",res); \n"
12892  #endif
12893  "upper = - 1;\n"
12894  #if RISCV64_DEBUG_CALL
12895  "printf(\"upper = %#lx\\n\",upper); \n"
12896  #endif
12897  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12898  #if RISCV64_DEBUG_CALL
12899  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12900  #endif
12901 "}\n"
12902 "flags = fget_flags();\n"
12903 #if RISCV64_DEBUG_CALL
12904 "printf(\"flags = %#x\\n\",flags); \n"
12905 #endif
12906 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12907 #if RISCV64_DEBUG_CALL
12908 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12909 #endif
12910 
12911  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12912 
12913 ;
12914 return true;
12915 },
12916 0,
12917 nullptr
12918 );
12919 //-------------------------------------------------------------------------------------------------------------------
12920 static InstructionDefinition fcvt_w_s_rd_frs1(
12921  ISA32_RISCV64,
12922  "fcvt.w.s",
12923  (uint32_t)0xc0000053,
12924  (uint32_t) 0xfff0007f,
12925  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12926  {
12927  etiss_uint64 rs1 = 0;
12928  static BitArrayRange R_rs1_0 (19,15);
12929  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12930  rs1 += rs1_0;
12931  etiss_uint64 rd = 0;
12932  static BitArrayRange R_rd_0 (11,7);
12933  etiss_uint64 rd_0 = R_rd_0.read(ba);
12934  rd += rd_0;
12935  etiss_uint64 rm = 0;
12936  static BitArrayRange R_rm_0 (14,12);
12937  etiss_uint64 rm_0 = R_rm_0.read(ba);
12938  rm += rm_0;
12939  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12940  partInit.getAffectedRegisters().add(reg_name[rd],64);
12941  partInit.getAffectedRegisters().add("instructionPointer",64);
12942  partInit.code() = std::string("//fcvt.w.s\n")+
12943  "etiss_uint32 temp = 0;\n"
12944  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12945  #if RISCV64_Pipeline1
12946  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12947  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12948  "etiss_uint32 num_stages = 4;\n"
12949  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12950  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12951  #endif
12952  #if RISCV64_Pipeline2
12953  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12954  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12955  "etiss_uint32 num_stages = 4;\n"
12956  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12957  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12958  #endif
12959 
12960  "etiss_uint32 flags = 0;\n"
12961  "etiss_uint32 frs1 = 0;\n"
12962 
12963 "if(64 == 32)\n"
12964 "{\n"
12965  "etiss_int32 cast_0 = fcvt_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n"
12966  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
12967  "{\n"
12968  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
12969  "}\n"
12970  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
12971  #if RISCV64_DEBUG_CALL
12972  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
12973  #endif
12974 "}\n"
12975 
12976 "else\n"
12977 "{\n"
12978  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12979  #if RISCV64_DEBUG_CALL
12980  "printf(\"frs1 = %#x\\n\",frs1); \n"
12981  #endif
12982  "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n"
12983  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
12984  "{\n"
12985  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
12986  "}\n"
12987  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
12988  #if RISCV64_DEBUG_CALL
12989  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
12990  #endif
12991 "}\n"
12992 "flags = fget_flags();\n"
12993 #if RISCV64_DEBUG_CALL
12994 "printf(\"flags = %#x\\n\",flags); \n"
12995 #endif
12996 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12997 #if RISCV64_DEBUG_CALL
12998 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12999 #endif
13000 
13001  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13002 
13003 ;
13004 return true;
13005 },
13006 0,
13007 nullptr
13008 );
13009 //-------------------------------------------------------------------------------------------------------------------
13010 static InstructionDefinition fcvt_wu_s_rd_frs1(
13011  ISA32_RISCV64,
13012  "fcvt.wu.s",
13013  (uint32_t)0xc0100053,
13014  (uint32_t) 0xfff0007f,
13015  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13016  {
13017  etiss_uint64 rs1 = 0;
13018  static BitArrayRange R_rs1_0 (19,15);
13019  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13020  rs1 += rs1_0;
13021  etiss_uint64 rd = 0;
13022  static BitArrayRange R_rd_0 (11,7);
13023  etiss_uint64 rd_0 = R_rd_0.read(ba);
13024  rd += rd_0;
13025  etiss_uint64 rm = 0;
13026  static BitArrayRange R_rm_0 (14,12);
13027  etiss_uint64 rm_0 = R_rm_0.read(ba);
13028  rm += rm_0;
13029  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13030  partInit.getAffectedRegisters().add(reg_name[rd],64);
13031  partInit.getAffectedRegisters().add("instructionPointer",64);
13032  partInit.code() = std::string("//fcvt.wu.s\n")+
13033  "etiss_uint32 temp = 0;\n"
13034  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13035  #if RISCV64_Pipeline1
13036  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13037  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13038  "etiss_uint32 num_stages = 4;\n"
13039  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13040  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13041  #endif
13042  #if RISCV64_Pipeline2
13043  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13044  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13045  "etiss_uint32 num_stages = 4;\n"
13046  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13047  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13048  #endif
13049 
13050  "etiss_uint32 flags = 0;\n"
13051  "etiss_uint32 frs1 = 0;\n"
13052 
13053 "if(64 == 32)\n"
13054 "{\n"
13055  "etiss_int32 cast_0 = fcvt_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n"
13056  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
13057  "{\n"
13058  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
13059  "}\n"
13060  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
13061  #if RISCV64_DEBUG_CALL
13062  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13063  #endif
13064 "}\n"
13065 
13066 "else\n"
13067 "{\n"
13068  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
13069  #if RISCV64_DEBUG_CALL
13070  "printf(\"frs1 = %#x\\n\",frs1); \n"
13071  #endif
13072  "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n"
13073  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
13074  "{\n"
13075  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
13076  "}\n"
13077  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
13078  #if RISCV64_DEBUG_CALL
13079  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13080  #endif
13081 "}\n"
13082 "flags = fget_flags();\n"
13083 #if RISCV64_DEBUG_CALL
13084 "printf(\"flags = %#x\\n\",flags); \n"
13085 #endif
13086 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13087 #if RISCV64_DEBUG_CALL
13088 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13089 #endif
13090 
13091  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13092 
13093 ;
13094 return true;
13095 },
13096 0,
13097 nullptr
13098 );
13099 //-------------------------------------------------------------------------------------------------------------------
13100 static InstructionDefinition fcvt_l_s_rd_frs1(
13101  ISA32_RISCV64,
13102  "fcvt.l.s",
13103  (uint32_t)0xc0200053,
13104  (uint32_t) 0xfff0007f,
13105  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13106  {
13107  etiss_uint64 rs1 = 0;
13108  static BitArrayRange R_rs1_0 (19,15);
13109  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13110  rs1 += rs1_0;
13111  etiss_uint64 rd = 0;
13112  static BitArrayRange R_rd_0 (11,7);
13113  etiss_uint64 rd_0 = R_rd_0.read(ba);
13114  rd += rd_0;
13115  etiss_uint64 rm = 0;
13116  static BitArrayRange R_rm_0 (14,12);
13117  etiss_uint64 rm_0 = R_rm_0.read(ba);
13118  rm += rm_0;
13119  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13120  partInit.getAffectedRegisters().add(reg_name[rd],64);
13121  partInit.getAffectedRegisters().add("instructionPointer",64);
13122  partInit.code() = std::string("//fcvt.l.s\n")+
13123  "etiss_uint32 temp = 0;\n"
13124  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13125  #if RISCV64_Pipeline1
13126  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13127  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13128  "etiss_uint32 num_stages = 4;\n"
13129  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13130  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13131  #endif
13132  #if RISCV64_Pipeline2
13133  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13134  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13135  "etiss_uint32 num_stages = 4;\n"
13136  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13137  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13138  #endif
13139 
13140  "etiss_uint64 res = 0;\n"
13141  "etiss_uint32 flags = 0;\n"
13142 
13143 "res = fcvt_32_64(unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]), (etiss_uint32)0, (" + toString(rm) + " & 0xff));\n"
13144 #if RISCV64_DEBUG_CALL
13145 "printf(\"res = %#lx\\n\",res); \n"
13146 #endif
13147 "etiss_int64 cast_0 = res; \n"
13148 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
13149 "{\n"
13150  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
13151 "}\n"
13152 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
13153 #if RISCV64_DEBUG_CALL
13154 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13155 #endif
13156 "flags = fget_flags();\n"
13157 #if RISCV64_DEBUG_CALL
13158 "printf(\"flags = %#x\\n\",flags); \n"
13159 #endif
13160 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13161 #if RISCV64_DEBUG_CALL
13162 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13163 #endif
13164 
13165  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13166 
13167 ;
13168 return true;
13169 },
13170 0,
13171 nullptr
13172 );
13173 //-------------------------------------------------------------------------------------------------------------------
13174 static InstructionDefinition fcvt_lu_s_rd_frs1(
13175  ISA32_RISCV64,
13176  "fcvt.lu.s",
13177  (uint32_t)0xc0300053,
13178  (uint32_t) 0xfff0007f,
13179  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13180  {
13181  etiss_uint64 rs1 = 0;
13182  static BitArrayRange R_rs1_0 (19,15);
13183  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13184  rs1 += rs1_0;
13185  etiss_uint64 rd = 0;
13186  static BitArrayRange R_rd_0 (11,7);
13187  etiss_uint64 rd_0 = R_rd_0.read(ba);
13188  rd += rd_0;
13189  etiss_uint64 rm = 0;
13190  static BitArrayRange R_rm_0 (14,12);
13191  etiss_uint64 rm_0 = R_rm_0.read(ba);
13192  rm += rm_0;
13193  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13194  partInit.getAffectedRegisters().add(reg_name[rd],64);
13195  partInit.getAffectedRegisters().add("instructionPointer",64);
13196  partInit.code() = std::string("//fcvt.lu.s\n")+
13197  "etiss_uint32 temp = 0;\n"
13198  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13199  #if RISCV64_Pipeline1
13200  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13201  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13202  "etiss_uint32 num_stages = 4;\n"
13203  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13204  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13205  #endif
13206  #if RISCV64_Pipeline2
13207  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13208  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13209  "etiss_uint32 num_stages = 4;\n"
13210  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13211  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13212  #endif
13213 
13214  "etiss_uint64 res = 0;\n"
13215  "etiss_uint32 flags = 0;\n"
13216 
13217 "res = fcvt_32_64(unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]), (etiss_uint32)1, (" + toString(rm) + " & 0xff));\n"
13218 #if RISCV64_DEBUG_CALL
13219 "printf(\"res = %#lx\\n\",res); \n"
13220 #endif
13221 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)res;\n"
13222 #if RISCV64_DEBUG_CALL
13223 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13224 #endif
13225 "flags = fget_flags();\n"
13226 #if RISCV64_DEBUG_CALL
13227 "printf(\"flags = %#x\\n\",flags); \n"
13228 #endif
13229 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13230 #if RISCV64_DEBUG_CALL
13231 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13232 #endif
13233 
13234  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13235 
13236 ;
13237 return true;
13238 },
13239 0,
13240 nullptr
13241 );
13242 //-------------------------------------------------------------------------------------------------------------------
13243 static InstructionDefinition feq_s_rd_frs1_frs2(
13244  ISA32_RISCV64,
13245  "feq.s",
13246  (uint32_t)0xa0002053,
13247  (uint32_t) 0xfe00707f,
13248  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13249  {
13250  etiss_uint64 rs2 = 0;
13251  static BitArrayRange R_rs2_0 (24,20);
13252  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
13253  rs2 += rs2_0;
13254  etiss_uint64 rs1 = 0;
13255  static BitArrayRange R_rs1_0 (19,15);
13256  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13257  rs1 += rs1_0;
13258  etiss_uint64 rd = 0;
13259  static BitArrayRange R_rd_0 (11,7);
13260  etiss_uint64 rd_0 = R_rd_0.read(ba);
13261  rd += rd_0;
13262  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13263  partInit.getAffectedRegisters().add(reg_name[rd],64);
13264  partInit.getAffectedRegisters().add("instructionPointer",64);
13265  partInit.code() = std::string("//feq.s\n")+
13266  "etiss_uint32 temp = 0;\n"
13267  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13268  #if RISCV64_Pipeline1
13269  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13270  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13271  "etiss_uint32 num_stages = 4;\n"
13272  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13273  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13274  #endif
13275  #if RISCV64_Pipeline2
13276  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13277  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13278  "etiss_uint32 num_stages = 4;\n"
13279  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13280  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13281  #endif
13282 
13283  "etiss_uint32 flags = 0;\n"
13284  "etiss_uint32 frs1 = 0;\n"
13285  "etiss_uint32 frs2 = 0;\n"
13286 
13287 "if(64 == 32)\n"
13288 "{\n"
13289  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)0);\n"
13290  #if RISCV64_DEBUG_CALL
13291  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13292  #endif
13293 "}\n"
13294 
13295 "else\n"
13296 "{\n"
13297  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
13298  #if RISCV64_DEBUG_CALL
13299  "printf(\"frs1 = %#x\\n\",frs1); \n"
13300  #endif
13301  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
13302  #if RISCV64_DEBUG_CALL
13303  "printf(\"frs2 = %#x\\n\",frs2); \n"
13304  #endif
13305  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)0);\n"
13306  #if RISCV64_DEBUG_CALL
13307  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13308  #endif
13309 "}\n"
13310 "flags = fget_flags();\n"
13311 #if RISCV64_DEBUG_CALL
13312 "printf(\"flags = %#x\\n\",flags); \n"
13313 #endif
13314 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13315 #if RISCV64_DEBUG_CALL
13316 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13317 #endif
13318 
13319  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13320 
13321 ;
13322 return true;
13323 },
13324 0,
13325 nullptr
13326 );
13327 //-------------------------------------------------------------------------------------------------------------------
13328 static InstructionDefinition flt_s_rd_frs1_frs2(
13329  ISA32_RISCV64,
13330  "flt.s",
13331  (uint32_t)0xa0001053,
13332  (uint32_t) 0xfe00707f,
13333  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13334  {
13335  etiss_uint64 rs2 = 0;
13336  static BitArrayRange R_rs2_0 (24,20);
13337  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
13338  rs2 += rs2_0;
13339  etiss_uint64 rs1 = 0;
13340  static BitArrayRange R_rs1_0 (19,15);
13341  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13342  rs1 += rs1_0;
13343  etiss_uint64 rd = 0;
13344  static BitArrayRange R_rd_0 (11,7);
13345  etiss_uint64 rd_0 = R_rd_0.read(ba);
13346  rd += rd_0;
13347  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13348  partInit.getAffectedRegisters().add(reg_name[rd],64);
13349  partInit.getAffectedRegisters().add("instructionPointer",64);
13350  partInit.code() = std::string("//flt.s\n")+
13351  "etiss_uint32 temp = 0;\n"
13352  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13353  #if RISCV64_Pipeline1
13354  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13355  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13356  "etiss_uint32 num_stages = 4;\n"
13357  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13358  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13359  #endif
13360  #if RISCV64_Pipeline2
13361  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13362  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13363  "etiss_uint32 num_stages = 4;\n"
13364  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13365  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13366  #endif
13367 
13368  "etiss_uint32 flags = 0;\n"
13369  "etiss_uint32 frs1 = 0;\n"
13370  "etiss_uint32 frs2 = 0;\n"
13371 
13372 "if(64 == 32)\n"
13373 "{\n"
13374  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)2);\n"
13375  #if RISCV64_DEBUG_CALL
13376  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13377  #endif
13378 "}\n"
13379 
13380 "else\n"
13381 "{\n"
13382  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
13383  #if RISCV64_DEBUG_CALL
13384  "printf(\"frs1 = %#x\\n\",frs1); \n"
13385  #endif
13386  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
13387  #if RISCV64_DEBUG_CALL
13388  "printf(\"frs2 = %#x\\n\",frs2); \n"
13389  #endif
13390  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)2);\n"
13391  #if RISCV64_DEBUG_CALL
13392  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13393  #endif
13394 "}\n"
13395 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = fcmp_s((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffff), (etiss_uint32)2);\n"
13396 #if RISCV64_DEBUG_CALL
13397 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13398 #endif
13399 "flags = fget_flags();\n"
13400 #if RISCV64_DEBUG_CALL
13401 "printf(\"flags = %#x\\n\",flags); \n"
13402 #endif
13403 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13404 #if RISCV64_DEBUG_CALL
13405 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13406 #endif
13407 
13408  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13409 
13410 ;
13411 return true;
13412 },
13413 0,
13414 nullptr
13415 );
13416 //-------------------------------------------------------------------------------------------------------------------
13417 static InstructionDefinition fle_s_rd_frs1_frs2(
13418  ISA32_RISCV64,
13419  "fle.s",
13420  (uint32_t)0xa0000053,
13421  (uint32_t) 0xfe00707f,
13422  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13423  {
13424  etiss_uint64 rs2 = 0;
13425  static BitArrayRange R_rs2_0 (24,20);
13426  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
13427  rs2 += rs2_0;
13428  etiss_uint64 rs1 = 0;
13429  static BitArrayRange R_rs1_0 (19,15);
13430  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13431  rs1 += rs1_0;
13432  etiss_uint64 rd = 0;
13433  static BitArrayRange R_rd_0 (11,7);
13434  etiss_uint64 rd_0 = R_rd_0.read(ba);
13435  rd += rd_0;
13436  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13437  partInit.getAffectedRegisters().add(reg_name[rd],64);
13438  partInit.getAffectedRegisters().add("instructionPointer",64);
13439  partInit.code() = std::string("//fle.s\n")+
13440  "etiss_uint32 temp = 0;\n"
13441  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13442  #if RISCV64_Pipeline1
13443  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13444  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13445  "etiss_uint32 num_stages = 4;\n"
13446  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13447  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13448  #endif
13449  #if RISCV64_Pipeline2
13450  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13451  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13452  "etiss_uint32 num_stages = 4;\n"
13453  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13454  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13455  #endif
13456 
13457  "etiss_uint32 flags = 0;\n"
13458  "etiss_uint32 frs1 = 0;\n"
13459  "etiss_uint32 frs2 = 0;\n"
13460 
13461 "if(64 == 32)\n"
13462 "{\n"
13463  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)1);\n"
13464  #if RISCV64_DEBUG_CALL
13465  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13466  #endif
13467 "}\n"
13468 
13469 "else\n"
13470 "{\n"
13471  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
13472  #if RISCV64_DEBUG_CALL
13473  "printf(\"frs1 = %#x\\n\",frs1); \n"
13474  #endif
13475  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
13476  #if RISCV64_DEBUG_CALL
13477  "printf(\"frs2 = %#x\\n\",frs2); \n"
13478  #endif
13479  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)1);\n"
13480  #if RISCV64_DEBUG_CALL
13481  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13482  #endif
13483 "}\n"
13484 "flags = fget_flags();\n"
13485 #if RISCV64_DEBUG_CALL
13486 "printf(\"flags = %#x\\n\",flags); \n"
13487 #endif
13488 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13489 #if RISCV64_DEBUG_CALL
13490 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13491 #endif
13492 
13493  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13494 
13495 ;
13496 return true;
13497 },
13498 0,
13499 nullptr
13500 );
13501 //-------------------------------------------------------------------------------------------------------------------
13502 static InstructionDefinition fclass_s_rd_frs1(
13503  ISA32_RISCV64,
13504  "fclass.s",
13505  (uint32_t)0xe0001053,
13506  (uint32_t) 0xfff0707f,
13507  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13508  {
13509  etiss_uint64 rs1 = 0;
13510  static BitArrayRange R_rs1_0 (19,15);
13511  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13512  rs1 += rs1_0;
13513  etiss_uint64 rd = 0;
13514  static BitArrayRange R_rd_0 (11,7);
13515  etiss_uint64 rd_0 = R_rd_0.read(ba);
13516  rd += rd_0;
13517  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13518  partInit.getAffectedRegisters().add(reg_name[rd],64);
13519  partInit.getAffectedRegisters().add("instructionPointer",64);
13520  partInit.code() = std::string("//fclass.s\n")+
13521  "etiss_uint32 temp = 0;\n"
13522  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13523  #if RISCV64_Pipeline1
13524  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13525  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13526  "etiss_uint32 num_stages = 4;\n"
13527  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13528  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13529  #endif
13530  #if RISCV64_Pipeline2
13531  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13532  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13533  "etiss_uint32 num_stages = 4;\n"
13534  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13535  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13536  #endif
13537 
13538 
13539 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = fclass_s(unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]));\n"
13540 #if RISCV64_DEBUG_CALL
13541 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13542 #endif
13543 
13544  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13545 
13546 ;
13547 return true;
13548 },
13549 0,
13550 nullptr
13551 );
13552 //-------------------------------------------------------------------------------------------------------------------
13553 static InstructionDefinition fmv_x_w_rd_frs1(
13554  ISA32_RISCV64,
13555  "fmv.x.w",
13556  (uint32_t)0xe0000053,
13557  (uint32_t) 0xfff0707f,
13558  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13559  {
13560  etiss_uint64 rs1 = 0;
13561  static BitArrayRange R_rs1_0 (19,15);
13562  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13563  rs1 += rs1_0;
13564  etiss_uint64 rd = 0;
13565  static BitArrayRange R_rd_0 (11,7);
13566  etiss_uint64 rd_0 = R_rd_0.read(ba);
13567  rd += rd_0;
13568  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13569  partInit.getRegisterDependencies().add(reg_name[rs1],64);
13570  partInit.getAffectedRegisters().add(reg_name[rd],64);
13571  partInit.getAffectedRegisters().add("instructionPointer",64);
13572  partInit.code() = std::string("//fmv.x.w\n")+
13573  "etiss_uint32 temp = 0;\n"
13574  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13575  #if RISCV64_Pipeline1
13576  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13577  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13578  "etiss_uint32 num_stages = 4;\n"
13579  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13580  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13581  #endif
13582  #if RISCV64_Pipeline2
13583  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13584  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13585  "etiss_uint32 num_stages = 4;\n"
13586  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13587  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13588  #endif
13589 
13590 
13591 "etiss_int64 cast_0 = (((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffff); \n"
13592 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
13593 "{\n"
13594  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
13595 "}\n"
13596 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
13597 #if RISCV64_DEBUG_CALL
13598 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13599 #endif
13600 
13601  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13602 
13603 ;
13604 return true;
13605 },
13606 0,
13607 nullptr
13608 );
13609 //-------------------------------------------------------------------------------------------------------------------
13610 static InstructionDefinition fcvt_s_w_rd_rs1(
13611  ISA32_RISCV64,
13612  "fcvt.s.w",
13613  (uint32_t)0xd0000053,
13614  (uint32_t) 0xfff0007f,
13615  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13616  {
13617  etiss_uint64 rs1 = 0;
13618  static BitArrayRange R_rs1_0 (19,15);
13619  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13620  rs1 += rs1_0;
13621  etiss_uint64 rd = 0;
13622  static BitArrayRange R_rd_0 (11,7);
13623  etiss_uint64 rd_0 = R_rd_0.read(ba);
13624  rd += rd_0;
13625  etiss_uint64 rm = 0;
13626  static BitArrayRange R_rm_0 (14,12);
13627  etiss_uint64 rm_0 = R_rm_0.read(ba);
13628  rm += rm_0;
13629  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13630  partInit.getAffectedRegisters().add(reg_name[rd],64);
13631  partInit.getAffectedRegisters().add("instructionPointer",64);
13632  partInit.code() = std::string("//fcvt.s.w\n")+
13633  "etiss_uint32 temp = 0;\n"
13634  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13635  #if RISCV64_Pipeline1
13636  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13637  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13638  "etiss_uint32 num_stages = 4;\n"
13639  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13640  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13641  #endif
13642  #if RISCV64_Pipeline2
13643  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13644  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13645  "etiss_uint32 num_stages = 4;\n"
13646  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13647  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13648  #endif
13649 
13650  "etiss_uint32 res = 0;\n"
13651  "etiss_int64 upper = 0;\n"
13652 
13653 "if(64 == 32)\n"
13654 "{\n"
13655  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fcvt_s((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n"
13656  #if RISCV64_DEBUG_CALL
13657  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13658  #endif
13659 "}\n"
13660 
13661 "else\n"
13662 "{\n"
13663  "res = fcvt_s((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n"
13664  #if RISCV64_DEBUG_CALL
13665  "printf(\"res = %#x\\n\",res); \n"
13666  #endif
13667  "upper = - 1;\n"
13668  #if RISCV64_DEBUG_CALL
13669  "printf(\"upper = %#lx\\n\",upper); \n"
13670  #endif
13671  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
13672  #if RISCV64_DEBUG_CALL
13673  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13674  #endif
13675 "}\n"
13676 
13677  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13678 
13679 ;
13680 return true;
13681 },
13682 0,
13683 nullptr
13684 );
13685 //-------------------------------------------------------------------------------------------------------------------
13686 static InstructionDefinition fcvt_s_wu_rd_rs1(
13687  ISA32_RISCV64,
13688  "fcvt.s.wu",
13689  (uint32_t)0xd0100053,
13690  (uint32_t) 0xfff0007f,
13691  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13692  {
13693  etiss_uint64 rs1 = 0;
13694  static BitArrayRange R_rs1_0 (19,15);
13695  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13696  rs1 += rs1_0;
13697  etiss_uint64 rd = 0;
13698  static BitArrayRange R_rd_0 (11,7);
13699  etiss_uint64 rd_0 = R_rd_0.read(ba);
13700  rd += rd_0;
13701  etiss_uint64 rm = 0;
13702  static BitArrayRange R_rm_0 (14,12);
13703  etiss_uint64 rm_0 = R_rm_0.read(ba);
13704  rm += rm_0;
13705  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13706  partInit.getAffectedRegisters().add(reg_name[rd],64);
13707  partInit.getAffectedRegisters().add("instructionPointer",64);
13708  partInit.code() = std::string("//fcvt.s.wu\n")+
13709  "etiss_uint32 temp = 0;\n"
13710  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13711  #if RISCV64_Pipeline1
13712  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13713  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13714  "etiss_uint32 num_stages = 4;\n"
13715  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13716  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13717  #endif
13718  #if RISCV64_Pipeline2
13719  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13720  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13721  "etiss_uint32 num_stages = 4;\n"
13722  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13723  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13724  #endif
13725 
13726  "etiss_uint32 res = 0;\n"
13727  "etiss_int64 upper = 0;\n"
13728 
13729 "if(64 == 32)\n"
13730 "{\n"
13731  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fcvt_s((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n"
13732  #if RISCV64_DEBUG_CALL
13733  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13734  #endif
13735 "}\n"
13736 
13737 "else\n"
13738 "{\n"
13739  "res = fcvt_s((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n"
13740  #if RISCV64_DEBUG_CALL
13741  "printf(\"res = %#x\\n\",res); \n"
13742  #endif
13743  "upper = - 1;\n"
13744  #if RISCV64_DEBUG_CALL
13745  "printf(\"upper = %#lx\\n\",upper); \n"
13746  #endif
13747  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
13748  #if RISCV64_DEBUG_CALL
13749  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13750  #endif
13751 "}\n"
13752 
13753  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13754 
13755 ;
13756 return true;
13757 },
13758 0,
13759 nullptr
13760 );
13761 //-------------------------------------------------------------------------------------------------------------------
13762 static InstructionDefinition fcvt_s_l_rd_xrs1(
13763  ISA32_RISCV64,
13764  "fcvt.s.l",
13765  (uint32_t)0xd0200053,
13766  (uint32_t) 0xfff0007f,
13767  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13768  {
13769  etiss_uint64 rs1 = 0;
13770  static BitArrayRange R_rs1_0 (19,15);
13771  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13772  rs1 += rs1_0;
13773  etiss_uint64 rd = 0;
13774  static BitArrayRange R_rd_0 (11,7);
13775  etiss_uint64 rd_0 = R_rd_0.read(ba);
13776  rd += rd_0;
13777  etiss_uint64 rm = 0;
13778  static BitArrayRange R_rm_0 (14,12);
13779  etiss_uint64 rm_0 = R_rm_0.read(ba);
13780  rm += rm_0;
13781  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13782  partInit.getAffectedRegisters().add(reg_name[rd],64);
13783  partInit.getAffectedRegisters().add("instructionPointer",64);
13784  partInit.code() = std::string("//fcvt.s.l\n")+
13785  "etiss_uint32 temp = 0;\n"
13786  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13787  #if RISCV64_Pipeline1
13788  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13789  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13790  "etiss_uint32 num_stages = 4;\n"
13791  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13792  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13793  #endif
13794  #if RISCV64_Pipeline2
13795  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13796  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13797  "etiss_uint32 num_stages = 4;\n"
13798  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13799  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13800  #endif
13801 
13802  "etiss_uint32 res = 0;\n"
13803  "etiss_int64 upper = 0;\n"
13804 
13805 "res = fcvt_64_32(*((RISCV64*)cpu)->X[" + toString(rs1) + "], (etiss_uint32)2);\n"
13806 #if RISCV64_DEBUG_CALL
13807 "printf(\"res = %#x\\n\",res); \n"
13808 #endif
13809 "if(64 == 32)\n"
13810 "{\n"
13811  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
13812  #if RISCV64_DEBUG_CALL
13813  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13814  #endif
13815 "}\n"
13816 
13817 "else\n"
13818 "{\n"
13819  "upper = - 1;\n"
13820  #if RISCV64_DEBUG_CALL
13821  "printf(\"upper = %#lx\\n\",upper); \n"
13822  #endif
13823  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
13824  #if RISCV64_DEBUG_CALL
13825  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13826  #endif
13827 "}\n"
13828 
13829  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13830 
13831 ;
13832 return true;
13833 },
13834 0,
13835 nullptr
13836 );
13837 //-------------------------------------------------------------------------------------------------------------------
13838 static InstructionDefinition fcvt_s_lu_rd_xrs1(
13839  ISA32_RISCV64,
13840  "fcvt.s.lu",
13841  (uint32_t)0xd0300053,
13842  (uint32_t) 0xfff0007f,
13843  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13844  {
13845  etiss_uint64 rs1 = 0;
13846  static BitArrayRange R_rs1_0 (19,15);
13847  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13848  rs1 += rs1_0;
13849  etiss_uint64 rd = 0;
13850  static BitArrayRange R_rd_0 (11,7);
13851  etiss_uint64 rd_0 = R_rd_0.read(ba);
13852  rd += rd_0;
13853  etiss_uint64 rm = 0;
13854  static BitArrayRange R_rm_0 (14,12);
13855  etiss_uint64 rm_0 = R_rm_0.read(ba);
13856  rm += rm_0;
13857  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13858  partInit.getAffectedRegisters().add(reg_name[rd],64);
13859  partInit.getAffectedRegisters().add("instructionPointer",64);
13860  partInit.code() = std::string("//fcvt.s.lu\n")+
13861  "etiss_uint32 temp = 0;\n"
13862  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13863  #if RISCV64_Pipeline1
13864  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13865  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13866  "etiss_uint32 num_stages = 4;\n"
13867  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13868  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13869  #endif
13870  #if RISCV64_Pipeline2
13871  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13872  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13873  "etiss_uint32 num_stages = 4;\n"
13874  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13875  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13876  #endif
13877 
13878  "etiss_uint32 res = 0;\n"
13879  "etiss_int64 upper = 0;\n"
13880 
13881 "res = fcvt_64_32(*((RISCV64*)cpu)->X[" + toString(rs1) + "], (etiss_uint32)3);\n"
13882 #if RISCV64_DEBUG_CALL
13883 "printf(\"res = %#x\\n\",res); \n"
13884 #endif
13885 "if(64 == 32)\n"
13886 "{\n"
13887  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
13888  #if RISCV64_DEBUG_CALL
13889  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13890  #endif
13891 "}\n"
13892 
13893 "else\n"
13894 "{\n"
13895  "upper = - 1;\n"
13896  #if RISCV64_DEBUG_CALL
13897  "printf(\"upper = %#lx\\n\",upper); \n"
13898  #endif
13899  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
13900  #if RISCV64_DEBUG_CALL
13901  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13902  #endif
13903 "}\n"
13904 
13905  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13906 
13907 ;
13908 return true;
13909 },
13910 0,
13911 nullptr
13912 );
13913 //-------------------------------------------------------------------------------------------------------------------
13914 static InstructionDefinition fmv_w_x_rd_rs1(
13915  ISA32_RISCV64,
13916  "fmv.w.x",
13917  (uint32_t)0xf0000053,
13918  (uint32_t) 0xfff0707f,
13919  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13920  {
13921  etiss_uint64 rs1 = 0;
13922  static BitArrayRange R_rs1_0 (19,15);
13923  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13924  rs1 += rs1_0;
13925  etiss_uint64 rd = 0;
13926  static BitArrayRange R_rd_0 (11,7);
13927  etiss_uint64 rd_0 = R_rd_0.read(ba);
13928  rd += rd_0;
13929  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13930  partInit.getRegisterDependencies().add(reg_name[rs1],64);
13931  partInit.getAffectedRegisters().add(reg_name[rd],64);
13932  partInit.getAffectedRegisters().add("instructionPointer",64);
13933  partInit.code() = std::string("//fmv.w.x\n")+
13934  "etiss_uint32 temp = 0;\n"
13935  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13936  #if RISCV64_Pipeline1
13937  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13938  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13939  "etiss_uint32 num_stages = 4;\n"
13940  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13941  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13942  #endif
13943  #if RISCV64_Pipeline2
13944  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13945  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13946  "etiss_uint32 num_stages = 4;\n"
13947  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13948  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13949  #endif
13950 
13951  "etiss_int64 upper = 0;\n"
13952 
13953 "if(64 == 32)\n"
13954 "{\n"
13955  "((RISCV64*)cpu)->F[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff);\n"
13956  #if RISCV64_DEBUG_CALL
13957  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13958  #endif
13959 "}\n"
13960 
13961 "else\n"
13962 "{\n"
13963  "upper = - 1;\n"
13964  #if RISCV64_DEBUG_CALL
13965  "printf(\"upper = %#lx\\n\",upper); \n"
13966  #endif
13967  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)(*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff));\n"
13968  #if RISCV64_DEBUG_CALL
13969  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13970  #endif
13971 "}\n"
13972 
13973  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13974 
13975 ;
13976 return true;
13977 },
13978 0,
13979 nullptr
13980 );
13981 //-------------------------------------------------------------------------------------------------------------------
13982 static InstructionDefinition fsub_d_rd_frs1_frs2(
13983  ISA32_RISCV64,
13984  "fsub.d",
13985  (uint32_t)0xa000053,
13986  (uint32_t) 0xfe00007f,
13987  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13988  {
13989  etiss_uint64 rs2 = 0;
13990  static BitArrayRange R_rs2_0 (24,20);
13991  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
13992  rs2 += rs2_0;
13993  etiss_uint64 rs1 = 0;
13994  static BitArrayRange R_rs1_0 (19,15);
13995  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13996  rs1 += rs1_0;
13997  etiss_uint64 rd = 0;
13998  static BitArrayRange R_rd_0 (11,7);
13999  etiss_uint64 rd_0 = R_rd_0.read(ba);
14000  rd += rd_0;
14001  etiss_uint64 rm = 0;
14002  static BitArrayRange R_rm_0 (14,12);
14003  etiss_uint64 rm_0 = R_rm_0.read(ba);
14004  rm += rm_0;
14005  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14006  partInit.getAffectedRegisters().add(reg_name[rd],64);
14007  partInit.getAffectedRegisters().add("instructionPointer",64);
14008  partInit.code() = std::string("//fsub.d\n")+
14009  "etiss_uint32 temp = 0;\n"
14010  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14011  #if RISCV64_Pipeline1
14012  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14013  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14014  "etiss_uint32 num_stages = 4;\n"
14015  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14016  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14017  #endif
14018  #if RISCV64_Pipeline2
14019  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14020  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14021  "etiss_uint32 num_stages = 4;\n"
14022  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14023  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14024  #endif
14025 
14026  "etiss_uint64 res = 0;\n"
14027  "etiss_int64 upper = 0;\n"
14028  "etiss_uint32 flags = 0;\n"
14029  "etiss_uint32 choose1 = 0;\n"
14030 
14031 "if(" + toString(rm) + " < 7)\n"
14032 "{\n"
14033  "choose1 = (" + toString(rm) + " & 0xff);\n"
14034  #if RISCV64_DEBUG_CALL
14035  "printf(\"choose1 = %#x\\n\",choose1); \n"
14036  #endif
14037 "}\n"
14038 
14039 "else\n"
14040 "{\n"
14041  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
14042  #if RISCV64_DEBUG_CALL
14043  "printf(\"choose1 = %#x\\n\",choose1); \n"
14044  #endif
14045 "}\n"
14046 "res = fsub_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n"
14047 #if RISCV64_DEBUG_CALL
14048 "printf(\"res = %#lx\\n\",res); \n"
14049 #endif
14050 "if(64 == 64)\n"
14051 "{\n"
14052  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14053  #if RISCV64_DEBUG_CALL
14054  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14055  #endif
14056 "}\n"
14057 
14058 "else\n"
14059 "{\n"
14060  "upper = - 1;\n"
14061  #if RISCV64_DEBUG_CALL
14062  "printf(\"upper = %#lx\\n\",upper); \n"
14063  #endif
14064  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14065  #if RISCV64_DEBUG_CALL
14066  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14067  #endif
14068 "}\n"
14069 "flags = fget_flags();\n"
14070 #if RISCV64_DEBUG_CALL
14071 "printf(\"flags = %#x\\n\",flags); \n"
14072 #endif
14073 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14074 #if RISCV64_DEBUG_CALL
14075 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14076 #endif
14077 
14078  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14079 
14080 ;
14081 return true;
14082 },
14083 0,
14084 nullptr
14085 );
14086 //-------------------------------------------------------------------------------------------------------------------
14087 static InstructionDefinition fdiv_d_rd_frs1_frs2(
14088  ISA32_RISCV64,
14089  "fdiv.d",
14090  (uint32_t)0x1a000053,
14091  (uint32_t) 0xfe00007f,
14092  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14093  {
14094  etiss_uint64 rs2 = 0;
14095  static BitArrayRange R_rs2_0 (24,20);
14096  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14097  rs2 += rs2_0;
14098  etiss_uint64 rs1 = 0;
14099  static BitArrayRange R_rs1_0 (19,15);
14100  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14101  rs1 += rs1_0;
14102  etiss_uint64 rd = 0;
14103  static BitArrayRange R_rd_0 (11,7);
14104  etiss_uint64 rd_0 = R_rd_0.read(ba);
14105  rd += rd_0;
14106  etiss_uint64 rm = 0;
14107  static BitArrayRange R_rm_0 (14,12);
14108  etiss_uint64 rm_0 = R_rm_0.read(ba);
14109  rm += rm_0;
14110  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14111  partInit.getAffectedRegisters().add(reg_name[rd],64);
14112  partInit.getAffectedRegisters().add("instructionPointer",64);
14113  partInit.code() = std::string("//fdiv.d\n")+
14114  "etiss_uint32 temp = 0;\n"
14115  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14116  #if RISCV64_Pipeline1
14117  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14118  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14119  "etiss_uint32 num_stages = 4;\n"
14120  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14121  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14122  #endif
14123  #if RISCV64_Pipeline2
14124  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14125  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14126  "etiss_uint32 num_stages = 4;\n"
14127  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14128  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14129  #endif
14130 
14131  "etiss_uint64 res = 0;\n"
14132  "etiss_int64 upper = 0;\n"
14133  "etiss_uint32 flags = 0;\n"
14134  "etiss_uint32 choose1 = 0;\n"
14135 
14136 "if(" + toString(rm) + " < 7)\n"
14137 "{\n"
14138  "choose1 = (" + toString(rm) + " & 0xff);\n"
14139  #if RISCV64_DEBUG_CALL
14140  "printf(\"choose1 = %#x\\n\",choose1); \n"
14141  #endif
14142 "}\n"
14143 
14144 "else\n"
14145 "{\n"
14146  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
14147  #if RISCV64_DEBUG_CALL
14148  "printf(\"choose1 = %#x\\n\",choose1); \n"
14149  #endif
14150 "}\n"
14151 "res = fdiv_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n"
14152 #if RISCV64_DEBUG_CALL
14153 "printf(\"res = %#lx\\n\",res); \n"
14154 #endif
14155 "if(64 == 64)\n"
14156 "{\n"
14157  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14158  #if RISCV64_DEBUG_CALL
14159  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14160  #endif
14161 "}\n"
14162 
14163 "else\n"
14164 "{\n"
14165  "upper = - 1;\n"
14166  #if RISCV64_DEBUG_CALL
14167  "printf(\"upper = %#lx\\n\",upper); \n"
14168  #endif
14169  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14170  #if RISCV64_DEBUG_CALL
14171  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14172  #endif
14173 "}\n"
14174 "flags = fget_flags();\n"
14175 #if RISCV64_DEBUG_CALL
14176 "printf(\"flags = %#x\\n\",flags); \n"
14177 #endif
14178 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14179 #if RISCV64_DEBUG_CALL
14180 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14181 #endif
14182 
14183  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14184 
14185 ;
14186 return true;
14187 },
14188 0,
14189 nullptr
14190 );
14191 //-------------------------------------------------------------------------------------------------------------------
14192 static InstructionDefinition fsqrt_d_rd_frs1(
14193  ISA32_RISCV64,
14194  "fsqrt.d",
14195  (uint32_t)0x5a000053,
14196  (uint32_t) 0xfff0007f,
14197  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14198  {
14199  etiss_uint64 rs1 = 0;
14200  static BitArrayRange R_rs1_0 (19,15);
14201  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14202  rs1 += rs1_0;
14203  etiss_uint64 rd = 0;
14204  static BitArrayRange R_rd_0 (11,7);
14205  etiss_uint64 rd_0 = R_rd_0.read(ba);
14206  rd += rd_0;
14207  etiss_uint64 rm = 0;
14208  static BitArrayRange R_rm_0 (14,12);
14209  etiss_uint64 rm_0 = R_rm_0.read(ba);
14210  rm += rm_0;
14211  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14212  partInit.getAffectedRegisters().add(reg_name[rd],64);
14213  partInit.getAffectedRegisters().add("instructionPointer",64);
14214  partInit.code() = std::string("//fsqrt.d\n")+
14215  "etiss_uint32 temp = 0;\n"
14216  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14217  #if RISCV64_Pipeline1
14218  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14219  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14220  "etiss_uint32 num_stages = 4;\n"
14221  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14222  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14223  #endif
14224  #if RISCV64_Pipeline2
14225  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14226  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14227  "etiss_uint32 num_stages = 4;\n"
14228  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14229  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14230  #endif
14231 
14232  "etiss_uint64 res = 0;\n"
14233  "etiss_int64 upper = 0;\n"
14234  "etiss_uint32 flags = 0;\n"
14235  "etiss_uint32 choose1 = 0;\n"
14236 
14237 "if(" + toString(rm) + " < 7)\n"
14238 "{\n"
14239  "choose1 = (" + toString(rm) + " & 0xff);\n"
14240  #if RISCV64_DEBUG_CALL
14241  "printf(\"choose1 = %#x\\n\",choose1); \n"
14242  #endif
14243 "}\n"
14244 
14245 "else\n"
14246 "{\n"
14247  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
14248  #if RISCV64_DEBUG_CALL
14249  "printf(\"choose1 = %#x\\n\",choose1); \n"
14250  #endif
14251 "}\n"
14252 "res = fsqrt_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), choose1);\n"
14253 #if RISCV64_DEBUG_CALL
14254 "printf(\"res = %#lx\\n\",res); \n"
14255 #endif
14256 "if(64 == 64)\n"
14257 "{\n"
14258  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14259  #if RISCV64_DEBUG_CALL
14260  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14261  #endif
14262 "}\n"
14263 
14264 "else\n"
14265 "{\n"
14266  "upper = - 1;\n"
14267  #if RISCV64_DEBUG_CALL
14268  "printf(\"upper = %#lx\\n\",upper); \n"
14269  #endif
14270  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14271  #if RISCV64_DEBUG_CALL
14272  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14273  #endif
14274 "}\n"
14275 "flags = fget_flags();\n"
14276 #if RISCV64_DEBUG_CALL
14277 "printf(\"flags = %#x\\n\",flags); \n"
14278 #endif
14279 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14280 #if RISCV64_DEBUG_CALL
14281 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14282 #endif
14283 
14284  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14285 
14286 ;
14287 return true;
14288 },
14289 0,
14290 nullptr
14291 );
14292 //-------------------------------------------------------------------------------------------------------------------
14293 static InstructionDefinition fsgnj_d_rd_frs1_frs2(
14294  ISA32_RISCV64,
14295  "fsgnj.d",
14296  (uint32_t)0x22000053,
14297  (uint32_t) 0xfe00707f,
14298  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14299  {
14300  etiss_uint64 rs2 = 0;
14301  static BitArrayRange R_rs2_0 (24,20);
14302  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14303  rs2 += rs2_0;
14304  etiss_uint64 rs1 = 0;
14305  static BitArrayRange R_rs1_0 (19,15);
14306  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14307  rs1 += rs1_0;
14308  etiss_uint64 rd = 0;
14309  static BitArrayRange R_rd_0 (11,7);
14310  etiss_uint64 rd_0 = R_rd_0.read(ba);
14311  rd += rd_0;
14312  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14313  partInit.getRegisterDependencies().add(reg_name[rs2],64);
14314  partInit.getRegisterDependencies().add(reg_name[rs1],64);
14315  partInit.getAffectedRegisters().add(reg_name[rd],64);
14316  partInit.getAffectedRegisters().add("instructionPointer",64);
14317  partInit.code() = std::string("//fsgnj.d\n")+
14318  "etiss_uint32 temp = 0;\n"
14319  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14320  #if RISCV64_Pipeline1
14321  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14322  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14323  "etiss_uint32 num_stages = 4;\n"
14324  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14325  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14326  #endif
14327  #if RISCV64_Pipeline2
14328  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14329  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14330  "etiss_uint32 num_stages = 4;\n"
14331  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14332  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14333  #endif
14334 
14335  "etiss_uint64 res = 0;\n"
14336  "etiss_int64 ONE = 0;\n"
14337  "etiss_int64 upper = 0;\n"
14338  "etiss_int64 MSK1 = 0;\n"
14339  "etiss_int64 MSK2 = 0;\n"
14340 
14341 "ONE = 1;\n"
14342 #if RISCV64_DEBUG_CALL
14343 "printf(\"ONE = %#lx\\n\",ONE); \n"
14344 #endif
14345 "MSK1 = (ONE << 63);\n"
14346 #if RISCV64_DEBUG_CALL
14347 "printf(\"MSK1 = %#lx\\n\",MSK1); \n"
14348 #endif
14349 "MSK2 = MSK1 - 1;\n"
14350 #if RISCV64_DEBUG_CALL
14351 "printf(\"MSK2 = %#lx\\n\",MSK2); \n"
14352 #endif
14353 "res = (((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff) & MSK2) | ((((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff) & MSK1));\n"
14354 #if RISCV64_DEBUG_CALL
14355 "printf(\"res = %#lx\\n\",res); \n"
14356 #endif
14357 "if(64 == 64)\n"
14358 "{\n"
14359  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14360  #if RISCV64_DEBUG_CALL
14361  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14362  #endif
14363 "}\n"
14364 
14365 "else\n"
14366 "{\n"
14367  "upper = - 1;\n"
14368  #if RISCV64_DEBUG_CALL
14369  "printf(\"upper = %#lx\\n\",upper); \n"
14370  #endif
14371  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14372  #if RISCV64_DEBUG_CALL
14373  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14374  #endif
14375 "}\n"
14376 
14377  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14378 
14379 ;
14380 return true;
14381 },
14382 0,
14383 nullptr
14384 );
14385 //-------------------------------------------------------------------------------------------------------------------
14386 static InstructionDefinition fsgnjn_d_rd_frs1_frs2(
14387  ISA32_RISCV64,
14388  "fsgnjn.d",
14389  (uint32_t)0x22001053,
14390  (uint32_t) 0xfe00707f,
14391  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14392  {
14393  etiss_uint64 rs2 = 0;
14394  static BitArrayRange R_rs2_0 (24,20);
14395  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14396  rs2 += rs2_0;
14397  etiss_uint64 rs1 = 0;
14398  static BitArrayRange R_rs1_0 (19,15);
14399  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14400  rs1 += rs1_0;
14401  etiss_uint64 rd = 0;
14402  static BitArrayRange R_rd_0 (11,7);
14403  etiss_uint64 rd_0 = R_rd_0.read(ba);
14404  rd += rd_0;
14405  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14406  partInit.getRegisterDependencies().add(reg_name[rs2],64);
14407  partInit.getRegisterDependencies().add(reg_name[rs1],64);
14408  partInit.getAffectedRegisters().add(reg_name[rd],64);
14409  partInit.getAffectedRegisters().add("instructionPointer",64);
14410  partInit.code() = std::string("//fsgnjn.d\n")+
14411  "etiss_uint32 temp = 0;\n"
14412  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14413  #if RISCV64_Pipeline1
14414  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14415  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14416  "etiss_uint32 num_stages = 4;\n"
14417  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14418  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14419  #endif
14420  #if RISCV64_Pipeline2
14421  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14422  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14423  "etiss_uint32 num_stages = 4;\n"
14424  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14425  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14426  #endif
14427 
14428  "etiss_uint64 res = 0;\n"
14429  "etiss_int64 ONE = 0;\n"
14430  "etiss_int64 upper = 0;\n"
14431  "etiss_int64 MSK1 = 0;\n"
14432  "etiss_int64 MSK2 = 0;\n"
14433 
14434 "ONE = 1;\n"
14435 #if RISCV64_DEBUG_CALL
14436 "printf(\"ONE = %#lx\\n\",ONE); \n"
14437 #endif
14438 "MSK1 = (ONE << 63);\n"
14439 #if RISCV64_DEBUG_CALL
14440 "printf(\"MSK1 = %#lx\\n\",MSK1); \n"
14441 #endif
14442 "MSK2 = MSK1 - 1;\n"
14443 #if RISCV64_DEBUG_CALL
14444 "printf(\"MSK2 = %#lx\\n\",MSK2); \n"
14445 #endif
14446 "res = (((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff) & MSK2) | (~(((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff) & MSK1))&0xffffffffffffffff;\n"
14447 #if RISCV64_DEBUG_CALL
14448 "printf(\"res = %#lx\\n\",res); \n"
14449 #endif
14450 "if(64 == 64)\n"
14451 "{\n"
14452  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14453  #if RISCV64_DEBUG_CALL
14454  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14455  #endif
14456 "}\n"
14457 
14458 "else\n"
14459 "{\n"
14460  "upper = - 1;\n"
14461  #if RISCV64_DEBUG_CALL
14462  "printf(\"upper = %#lx\\n\",upper); \n"
14463  #endif
14464  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14465  #if RISCV64_DEBUG_CALL
14466  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14467  #endif
14468 "}\n"
14469 
14470  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14471 
14472 ;
14473 return true;
14474 },
14475 0,
14476 nullptr
14477 );
14478 //-------------------------------------------------------------------------------------------------------------------
14479 static InstructionDefinition fsgnjx_d_rd_frs1_frs2(
14480  ISA32_RISCV64,
14481  "fsgnjx.d",
14482  (uint32_t)0x22002053,
14483  (uint32_t) 0xfe00707f,
14484  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14485  {
14486  etiss_uint64 rs2 = 0;
14487  static BitArrayRange R_rs2_0 (24,20);
14488  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14489  rs2 += rs2_0;
14490  etiss_uint64 rs1 = 0;
14491  static BitArrayRange R_rs1_0 (19,15);
14492  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14493  rs1 += rs1_0;
14494  etiss_uint64 rd = 0;
14495  static BitArrayRange R_rd_0 (11,7);
14496  etiss_uint64 rd_0 = R_rd_0.read(ba);
14497  rd += rd_0;
14498  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14499  partInit.getRegisterDependencies().add(reg_name[rs2],64);
14500  partInit.getRegisterDependencies().add(reg_name[rs1],64);
14501  partInit.getAffectedRegisters().add(reg_name[rd],64);
14502  partInit.getAffectedRegisters().add("instructionPointer",64);
14503  partInit.code() = std::string("//fsgnjx.d\n")+
14504  "etiss_uint32 temp = 0;\n"
14505  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14506  #if RISCV64_Pipeline1
14507  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14508  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14509  "etiss_uint32 num_stages = 4;\n"
14510  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14511  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14512  #endif
14513  #if RISCV64_Pipeline2
14514  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14515  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14516  "etiss_uint32 num_stages = 4;\n"
14517  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14518  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14519  #endif
14520 
14521  "etiss_uint64 res = 0;\n"
14522  "etiss_int64 ONE = 0;\n"
14523  "etiss_int64 upper = 0;\n"
14524  "etiss_int64 MSK1 = 0;\n"
14525 
14526 "ONE = 1;\n"
14527 #if RISCV64_DEBUG_CALL
14528 "printf(\"ONE = %#lx\\n\",ONE); \n"
14529 #endif
14530 "MSK1 = (ONE << 63);\n"
14531 #if RISCV64_DEBUG_CALL
14532 "printf(\"MSK1 = %#lx\\n\",MSK1); \n"
14533 #endif
14534 "res = ((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff) ^ ((((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff) & MSK1));\n"
14535 #if RISCV64_DEBUG_CALL
14536 "printf(\"res = %#lx\\n\",res); \n"
14537 #endif
14538 "if(64 == 64)\n"
14539 "{\n"
14540  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14541  #if RISCV64_DEBUG_CALL
14542  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14543  #endif
14544 "}\n"
14545 
14546 "else\n"
14547 "{\n"
14548  "upper = - 1;\n"
14549  #if RISCV64_DEBUG_CALL
14550  "printf(\"upper = %#lx\\n\",upper); \n"
14551  #endif
14552  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14553  #if RISCV64_DEBUG_CALL
14554  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14555  #endif
14556 "}\n"
14557 
14558  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14559 
14560 ;
14561 return true;
14562 },
14563 0,
14564 nullptr
14565 );
14566 //-------------------------------------------------------------------------------------------------------------------
14567 static InstructionDefinition fmin_d_rd_frs1_frs2(
14568  ISA32_RISCV64,
14569  "fmin.d",
14570  (uint32_t)0x2a000053,
14571  (uint32_t) 0xfe00707f,
14572  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14573  {
14574  etiss_uint64 rs2 = 0;
14575  static BitArrayRange R_rs2_0 (24,20);
14576  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14577  rs2 += rs2_0;
14578  etiss_uint64 rs1 = 0;
14579  static BitArrayRange R_rs1_0 (19,15);
14580  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14581  rs1 += rs1_0;
14582  etiss_uint64 rd = 0;
14583  static BitArrayRange R_rd_0 (11,7);
14584  etiss_uint64 rd_0 = R_rd_0.read(ba);
14585  rd += rd_0;
14586  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14587  partInit.getAffectedRegisters().add(reg_name[rd],64);
14588  partInit.getAffectedRegisters().add("instructionPointer",64);
14589  partInit.code() = std::string("//fmin.d\n")+
14590  "etiss_uint32 temp = 0;\n"
14591  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14592  #if RISCV64_Pipeline1
14593  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14594  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14595  "etiss_uint32 num_stages = 4;\n"
14596  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14597  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14598  #endif
14599  #if RISCV64_Pipeline2
14600  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14601  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14602  "etiss_uint32 num_stages = 4;\n"
14603  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14604  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14605  #endif
14606 
14607  "etiss_uint64 res = 0;\n"
14608  "etiss_int64 upper = 0;\n"
14609  "etiss_uint32 flags = 0;\n"
14610 
14611 "res = fsel_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)0);\n"
14612 #if RISCV64_DEBUG_CALL
14613 "printf(\"res = %#lx\\n\",res); \n"
14614 #endif
14615 "if(64 == 64)\n"
14616 "{\n"
14617  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14618  #if RISCV64_DEBUG_CALL
14619  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14620  #endif
14621 "}\n"
14622 
14623 "else\n"
14624 "{\n"
14625  "upper = - 1;\n"
14626  #if RISCV64_DEBUG_CALL
14627  "printf(\"upper = %#lx\\n\",upper); \n"
14628  #endif
14629  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14630  #if RISCV64_DEBUG_CALL
14631  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14632  #endif
14633 "}\n"
14634 "flags = fget_flags();\n"
14635 #if RISCV64_DEBUG_CALL
14636 "printf(\"flags = %#x\\n\",flags); \n"
14637 #endif
14638 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14639 #if RISCV64_DEBUG_CALL
14640 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14641 #endif
14642 
14643  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14644 
14645 ;
14646 return true;
14647 },
14648 0,
14649 nullptr
14650 );
14651 //-------------------------------------------------------------------------------------------------------------------
14652 static InstructionDefinition fmax_d_rd_frs1_frs2(
14653  ISA32_RISCV64,
14654  "fmax.d",
14655  (uint32_t)0x2a001053,
14656  (uint32_t) 0xfe00707f,
14657  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14658  {
14659  etiss_uint64 rs2 = 0;
14660  static BitArrayRange R_rs2_0 (24,20);
14661  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14662  rs2 += rs2_0;
14663  etiss_uint64 rs1 = 0;
14664  static BitArrayRange R_rs1_0 (19,15);
14665  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14666  rs1 += rs1_0;
14667  etiss_uint64 rd = 0;
14668  static BitArrayRange R_rd_0 (11,7);
14669  etiss_uint64 rd_0 = R_rd_0.read(ba);
14670  rd += rd_0;
14671  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14672  partInit.getAffectedRegisters().add(reg_name[rd],64);
14673  partInit.getAffectedRegisters().add("instructionPointer",64);
14674  partInit.code() = std::string("//fmax.d\n")+
14675  "etiss_uint32 temp = 0;\n"
14676  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14677  #if RISCV64_Pipeline1
14678  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14679  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14680  "etiss_uint32 num_stages = 4;\n"
14681  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14682  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14683  #endif
14684  #if RISCV64_Pipeline2
14685  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14686  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14687  "etiss_uint32 num_stages = 4;\n"
14688  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14689  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14690  #endif
14691 
14692  "etiss_uint64 res = 0;\n"
14693  "etiss_int64 upper = 0;\n"
14694  "etiss_uint32 flags = 0;\n"
14695 
14696 "res = fsel_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)1);\n"
14697 #if RISCV64_DEBUG_CALL
14698 "printf(\"res = %#lx\\n\",res); \n"
14699 #endif
14700 "if(64 == 64)\n"
14701 "{\n"
14702  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14703  #if RISCV64_DEBUG_CALL
14704  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14705  #endif
14706 "}\n"
14707 
14708 "else\n"
14709 "{\n"
14710  "upper = - 1;\n"
14711  #if RISCV64_DEBUG_CALL
14712  "printf(\"upper = %#lx\\n\",upper); \n"
14713  #endif
14714  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14715  #if RISCV64_DEBUG_CALL
14716  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14717  #endif
14718 "}\n"
14719 "flags = fget_flags();\n"
14720 #if RISCV64_DEBUG_CALL
14721 "printf(\"flags = %#x\\n\",flags); \n"
14722 #endif
14723 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14724 #if RISCV64_DEBUG_CALL
14725 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14726 #endif
14727 
14728  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14729 
14730 ;
14731 return true;
14732 },
14733 0,
14734 nullptr
14735 );
14736 //-------------------------------------------------------------------------------------------------------------------
14737 static InstructionDefinition fcvt_d_s_rd_frs1(
14738  ISA32_RISCV64,
14739  "fcvt.d.s",
14740  (uint32_t)0x42000053,
14741  (uint32_t) 0xfff0007f,
14742  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14743  {
14744  etiss_uint64 rs1 = 0;
14745  static BitArrayRange R_rs1_0 (19,15);
14746  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14747  rs1 += rs1_0;
14748  etiss_uint64 rd = 0;
14749  static BitArrayRange R_rd_0 (11,7);
14750  etiss_uint64 rd_0 = R_rd_0.read(ba);
14751  rd += rd_0;
14752  etiss_uint64 rm = 0;
14753  static BitArrayRange R_rm_0 (14,12);
14754  etiss_uint64 rm_0 = R_rm_0.read(ba);
14755  rm += rm_0;
14756  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14757  partInit.getAffectedRegisters().add(reg_name[rd],64);
14758  partInit.getAffectedRegisters().add("instructionPointer",64);
14759  partInit.code() = std::string("//fcvt.d.s\n")+
14760  "etiss_uint32 temp = 0;\n"
14761  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14762  #if RISCV64_Pipeline1
14763  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14764  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14765  "etiss_uint32 num_stages = 4;\n"
14766  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14767  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14768  #endif
14769  #if RISCV64_Pipeline2
14770  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14771  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14772  "etiss_uint32 num_stages = 4;\n"
14773  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14774  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14775  #endif
14776 
14777  "etiss_uint64 res = 0;\n"
14778  "etiss_int64 upper = 0;\n"
14779 
14780 "res = fconv_f2d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffff), (" + toString(rm) + " & 0xff));\n"
14781 #if RISCV64_DEBUG_CALL
14782 "printf(\"res = %#lx\\n\",res); \n"
14783 #endif
14784 "if(64 == 64)\n"
14785 "{\n"
14786  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14787  #if RISCV64_DEBUG_CALL
14788  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14789  #endif
14790 "}\n"
14791 
14792 "else\n"
14793 "{\n"
14794  "upper = - 1;\n"
14795  #if RISCV64_DEBUG_CALL
14796  "printf(\"upper = %#lx\\n\",upper); \n"
14797  #endif
14798  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14799  #if RISCV64_DEBUG_CALL
14800  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14801  #endif
14802 "}\n"
14803 
14804  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14805 
14806 ;
14807 return true;
14808 },
14809 0,
14810 nullptr
14811 );
14812 //-------------------------------------------------------------------------------------------------------------------
14813 static InstructionDefinition feq_d_rd_frs1_frs2(
14814  ISA32_RISCV64,
14815  "feq.d",
14816  (uint32_t)0xa2002053,
14817  (uint32_t) 0xfe00707f,
14818  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14819  {
14820  etiss_uint64 rs2 = 0;
14821  static BitArrayRange R_rs2_0 (24,20);
14822  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14823  rs2 += rs2_0;
14824  etiss_uint64 rs1 = 0;
14825  static BitArrayRange R_rs1_0 (19,15);
14826  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14827  rs1 += rs1_0;
14828  etiss_uint64 rd = 0;
14829  static BitArrayRange R_rd_0 (11,7);
14830  etiss_uint64 rd_0 = R_rd_0.read(ba);
14831  rd += rd_0;
14832  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14833  partInit.getAffectedRegisters().add(reg_name[rd],64);
14834  partInit.getAffectedRegisters().add("instructionPointer",64);
14835  partInit.code() = std::string("//feq.d\n")+
14836  "etiss_uint32 temp = 0;\n"
14837  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14838  #if RISCV64_Pipeline1
14839  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14840  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14841  "etiss_uint32 num_stages = 4;\n"
14842  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14843  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14844  #endif
14845  #if RISCV64_Pipeline2
14846  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14847  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14848  "etiss_uint32 num_stages = 4;\n"
14849  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14850  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14851  #endif
14852 
14853  "etiss_uint32 flags = 0;\n"
14854 
14855 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)0);\n"
14856 #if RISCV64_DEBUG_CALL
14857 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
14858 #endif
14859 "flags = fget_flags();\n"
14860 #if RISCV64_DEBUG_CALL
14861 "printf(\"flags = %#x\\n\",flags); \n"
14862 #endif
14863 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14864 #if RISCV64_DEBUG_CALL
14865 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14866 #endif
14867 
14868  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14869 
14870 ;
14871 return true;
14872 },
14873 0,
14874 nullptr
14875 );
14876 //-------------------------------------------------------------------------------------------------------------------
14877 static InstructionDefinition flt_d_rd_frs1_frs2(
14878  ISA32_RISCV64,
14879  "flt.d",
14880  (uint32_t)0xa2001053,
14881  (uint32_t) 0xfe00707f,
14882  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14883  {
14884  etiss_uint64 rs2 = 0;
14885  static BitArrayRange R_rs2_0 (24,20);
14886  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14887  rs2 += rs2_0;
14888  etiss_uint64 rs1 = 0;
14889  static BitArrayRange R_rs1_0 (19,15);
14890  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14891  rs1 += rs1_0;
14892  etiss_uint64 rd = 0;
14893  static BitArrayRange R_rd_0 (11,7);
14894  etiss_uint64 rd_0 = R_rd_0.read(ba);
14895  rd += rd_0;
14896  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14897  partInit.getAffectedRegisters().add(reg_name[rd],64);
14898  partInit.getAffectedRegisters().add("instructionPointer",64);
14899  partInit.code() = std::string("//flt.d\n")+
14900  "etiss_uint32 temp = 0;\n"
14901  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14902  #if RISCV64_Pipeline1
14903  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14904  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14905  "etiss_uint32 num_stages = 4;\n"
14906  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14907  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14908  #endif
14909  #if RISCV64_Pipeline2
14910  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14911  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14912  "etiss_uint32 num_stages = 4;\n"
14913  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14914  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14915  #endif
14916 
14917  "etiss_uint32 flags = 0;\n"
14918 
14919 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)2);\n"
14920 #if RISCV64_DEBUG_CALL
14921 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
14922 #endif
14923 "flags = fget_flags();\n"
14924 #if RISCV64_DEBUG_CALL
14925 "printf(\"flags = %#x\\n\",flags); \n"
14926 #endif
14927 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14928 #if RISCV64_DEBUG_CALL
14929 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14930 #endif
14931 
14932  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14933 
14934 ;
14935 return true;
14936 },
14937 0,
14938 nullptr
14939 );
14940 //-------------------------------------------------------------------------------------------------------------------
14941 static InstructionDefinition fle_d_rd_frs1_frs2(
14942  ISA32_RISCV64,
14943  "fle.d",
14944  (uint32_t)0xa2000053,
14945  (uint32_t) 0xfe00707f,
14946  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14947  {
14948  etiss_uint64 rs2 = 0;
14949  static BitArrayRange R_rs2_0 (24,20);
14950  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14951  rs2 += rs2_0;
14952  etiss_uint64 rs1 = 0;
14953  static BitArrayRange R_rs1_0 (19,15);
14954  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14955  rs1 += rs1_0;
14956  etiss_uint64 rd = 0;
14957  static BitArrayRange R_rd_0 (11,7);
14958  etiss_uint64 rd_0 = R_rd_0.read(ba);
14959  rd += rd_0;
14960  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14961  partInit.getAffectedRegisters().add(reg_name[rd],64);
14962  partInit.getAffectedRegisters().add("instructionPointer",64);
14963  partInit.code() = std::string("//fle.d\n")+
14964  "etiss_uint32 temp = 0;\n"
14965  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14966  #if RISCV64_Pipeline1
14967  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14968  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14969  "etiss_uint32 num_stages = 4;\n"
14970  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14971  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14972  #endif
14973  #if RISCV64_Pipeline2
14974  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14975  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14976  "etiss_uint32 num_stages = 4;\n"
14977  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14978  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14979  #endif
14980 
14981  "etiss_uint32 flags = 0;\n"
14982 
14983 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)1);\n"
14984 #if RISCV64_DEBUG_CALL
14985 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
14986 #endif
14987 "flags = fget_flags();\n"
14988 #if RISCV64_DEBUG_CALL
14989 "printf(\"flags = %#x\\n\",flags); \n"
14990 #endif
14991 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14992 #if RISCV64_DEBUG_CALL
14993 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14994 #endif
14995 
14996  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14997 
14998 ;
14999 return true;
15000 },
15001 0,
15002 nullptr
15003 );
15004 //-------------------------------------------------------------------------------------------------------------------
15005 static InstructionDefinition fclass_d_rd_frs1(
15006  ISA32_RISCV64,
15007  "fclass.d",
15008  (uint32_t)0xe2001053,
15009  (uint32_t) 0xfff0707f,
15010  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15011  {
15012  etiss_uint64 rs1 = 0;
15013  static BitArrayRange R_rs1_0 (19,15);
15014  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15015  rs1 += rs1_0;
15016  etiss_uint64 rd = 0;
15017  static BitArrayRange R_rd_0 (11,7);
15018  etiss_uint64 rd_0 = R_rd_0.read(ba);
15019  rd += rd_0;
15020  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15021  partInit.getAffectedRegisters().add(reg_name[rd],64);
15022  partInit.getAffectedRegisters().add("instructionPointer",64);
15023  partInit.code() = std::string("//fclass.d\n")+
15024  "etiss_uint32 temp = 0;\n"
15025  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15026  #if RISCV64_Pipeline1
15027  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15028  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15029  "etiss_uint32 num_stages = 4;\n"
15030  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15031  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15032  #endif
15033  #if RISCV64_Pipeline2
15034  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15035  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15036  "etiss_uint32 num_stages = 4;\n"
15037  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15038  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15039  #endif
15040 
15041 
15042 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = fclass_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff));\n"
15043 #if RISCV64_DEBUG_CALL
15044 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15045 #endif
15046 
15047  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15048 
15049 ;
15050 return true;
15051 },
15052 0,
15053 nullptr
15054 );
15055 //-------------------------------------------------------------------------------------------------------------------
15056 static InstructionDefinition fmv_x_d_rd_frs1(
15057  ISA32_RISCV64,
15058  "fmv.x.d",
15059  (uint32_t)0xe2000053,
15060  (uint32_t) 0xfff0707f,
15061  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15062  {
15063  etiss_uint64 rs1 = 0;
15064  static BitArrayRange R_rs1_0 (19,15);
15065  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15066  rs1 += rs1_0;
15067  etiss_uint64 rd = 0;
15068  static BitArrayRange R_rd_0 (11,7);
15069  etiss_uint64 rd_0 = R_rd_0.read(ba);
15070  rd += rd_0;
15071  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15072  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15073  partInit.getAffectedRegisters().add(reg_name[rd],64);
15074  partInit.getAffectedRegisters().add("instructionPointer",64);
15075  partInit.code() = std::string("//fmv.x.d\n")+
15076  "etiss_uint32 temp = 0;\n"
15077  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15078  #if RISCV64_Pipeline1
15079  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15080  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15081  "etiss_uint32 num_stages = 4;\n"
15082  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15083  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15084  #endif
15085  #if RISCV64_Pipeline2
15086  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15087  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15088  "etiss_uint32 num_stages = 4;\n"
15089  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15090  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15091  #endif
15092 
15093 
15094 "etiss_int64 cast_0 = ((RISCV64*)cpu)->F[" + toString(rs1) + "]; \n"
15095 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15096 "{\n"
15097  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15098 "}\n"
15099 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15100 #if RISCV64_DEBUG_CALL
15101 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15102 #endif
15103 
15104  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15105 
15106 ;
15107 return true;
15108 },
15109 0,
15110 nullptr
15111 );
15112 //-------------------------------------------------------------------------------------------------------------------
15113 static InstructionDefinition fcvt_w_d_rd_frs1(
15114  ISA32_RISCV64,
15115  "fcvt.w.d",
15116  (uint32_t)0xc2000053,
15117  (uint32_t) 0xfff0007f,
15118  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15119  {
15120  etiss_uint64 rs1 = 0;
15121  static BitArrayRange R_rs1_0 (19,15);
15122  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15123  rs1 += rs1_0;
15124  etiss_uint64 rd = 0;
15125  static BitArrayRange R_rd_0 (11,7);
15126  etiss_uint64 rd_0 = R_rd_0.read(ba);
15127  rd += rd_0;
15128  etiss_uint64 rm = 0;
15129  static BitArrayRange R_rm_0 (14,12);
15130  etiss_uint64 rm_0 = R_rm_0.read(ba);
15131  rm += rm_0;
15132  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15133  partInit.getAffectedRegisters().add(reg_name[rd],64);
15134  partInit.getAffectedRegisters().add("instructionPointer",64);
15135  partInit.code() = std::string("//fcvt.w.d\n")+
15136  "etiss_uint32 temp = 0;\n"
15137  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15138  #if RISCV64_Pipeline1
15139  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15140  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15141  "etiss_uint32 num_stages = 4;\n"
15142  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15143  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15144  #endif
15145  #if RISCV64_Pipeline2
15146  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15147  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15148  "etiss_uint32 num_stages = 4;\n"
15149  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15150  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15151  #endif
15152 
15153  "etiss_uint32 flags = 0;\n"
15154 
15155 "etiss_int32 cast_0 = fcvt_64_32((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n"
15156 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
15157 "{\n"
15158  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
15159 "}\n"
15160 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15161 #if RISCV64_DEBUG_CALL
15162 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15163 #endif
15164 "flags = fget_flags();\n"
15165 #if RISCV64_DEBUG_CALL
15166 "printf(\"flags = %#x\\n\",flags); \n"
15167 #endif
15168 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
15169 #if RISCV64_DEBUG_CALL
15170 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
15171 #endif
15172 
15173  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15174 
15175 ;
15176 return true;
15177 },
15178 0,
15179 nullptr
15180 );
15181 //-------------------------------------------------------------------------------------------------------------------
15182 static InstructionDefinition fcvt_wu_d_rd_frs1(
15183  ISA32_RISCV64,
15184  "fcvt.wu.d",
15185  (uint32_t)0xc2100053,
15186  (uint32_t) 0xfff0007f,
15187  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15188  {
15189  etiss_uint64 rs1 = 0;
15190  static BitArrayRange R_rs1_0 (19,15);
15191  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15192  rs1 += rs1_0;
15193  etiss_uint64 rd = 0;
15194  static BitArrayRange R_rd_0 (11,7);
15195  etiss_uint64 rd_0 = R_rd_0.read(ba);
15196  rd += rd_0;
15197  etiss_uint64 rm = 0;
15198  static BitArrayRange R_rm_0 (14,12);
15199  etiss_uint64 rm_0 = R_rm_0.read(ba);
15200  rm += rm_0;
15201  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15202  partInit.getAffectedRegisters().add(reg_name[rd],64);
15203  partInit.getAffectedRegisters().add("instructionPointer",64);
15204  partInit.code() = std::string("//fcvt.wu.d\n")+
15205  "etiss_uint32 temp = 0;\n"
15206  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15207  #if RISCV64_Pipeline1
15208  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15209  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15210  "etiss_uint32 num_stages = 4;\n"
15211  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15212  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15213  #endif
15214  #if RISCV64_Pipeline2
15215  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15216  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15217  "etiss_uint32 num_stages = 4;\n"
15218  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15219  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15220  #endif
15221 
15222  "etiss_uint32 flags = 0;\n"
15223 
15224 "etiss_int32 cast_0 = fcvt_64_32((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n"
15225 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
15226 "{\n"
15227  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
15228 "}\n"
15229 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15230 #if RISCV64_DEBUG_CALL
15231 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15232 #endif
15233 "flags = fget_flags();\n"
15234 #if RISCV64_DEBUG_CALL
15235 "printf(\"flags = %#x\\n\",flags); \n"
15236 #endif
15237 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
15238 #if RISCV64_DEBUG_CALL
15239 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
15240 #endif
15241 
15242  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15243 
15244 ;
15245 return true;
15246 },
15247 0,
15248 nullptr
15249 );
15250 //-------------------------------------------------------------------------------------------------------------------
15251 static InstructionDefinition fcvt_l_d_rd_frs1(
15252  ISA32_RISCV64,
15253  "fcvt.l.d",
15254  (uint32_t)0xc2200053,
15255  (uint32_t) 0xfff0007f,
15256  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15257  {
15258  etiss_uint64 rs1 = 0;
15259  static BitArrayRange R_rs1_0 (19,15);
15260  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15261  rs1 += rs1_0;
15262  etiss_uint64 rd = 0;
15263  static BitArrayRange R_rd_0 (11,7);
15264  etiss_uint64 rd_0 = R_rd_0.read(ba);
15265  rd += rd_0;
15266  etiss_uint64 rm = 0;
15267  static BitArrayRange R_rm_0 (14,12);
15268  etiss_uint64 rm_0 = R_rm_0.read(ba);
15269  rm += rm_0;
15270  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15271  partInit.getAffectedRegisters().add(reg_name[rd],64);
15272  partInit.getAffectedRegisters().add("instructionPointer",64);
15273  partInit.code() = std::string("//fcvt.l.d\n")+
15274  "etiss_uint32 temp = 0;\n"
15275  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15276  #if RISCV64_Pipeline1
15277  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15278  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15279  "etiss_uint32 num_stages = 4;\n"
15280  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15281  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15282  #endif
15283  #if RISCV64_Pipeline2
15284  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15285  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15286  "etiss_uint32 num_stages = 4;\n"
15287  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15288  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15289  #endif
15290 
15291  "etiss_uint32 flags = 0;\n"
15292 
15293 "etiss_int64 cast_0 = fcvt_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n"
15294 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15295 "{\n"
15296  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15297 "}\n"
15298 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15299 #if RISCV64_DEBUG_CALL
15300 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15301 #endif
15302 "flags = fget_flags();\n"
15303 #if RISCV64_DEBUG_CALL
15304 "printf(\"flags = %#x\\n\",flags); \n"
15305 #endif
15306 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
15307 #if RISCV64_DEBUG_CALL
15308 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
15309 #endif
15310 
15311  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15312 
15313 ;
15314 return true;
15315 },
15316 0,
15317 nullptr
15318 );
15319 //-------------------------------------------------------------------------------------------------------------------
15320 static InstructionDefinition fcvt_lu_d_rd_frs1(
15321  ISA32_RISCV64,
15322  "fcvt.lu.d",
15323  (uint32_t)0xc2300053,
15324  (uint32_t) 0xfff0007f,
15325  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15326  {
15327  etiss_uint64 rs1 = 0;
15328  static BitArrayRange R_rs1_0 (19,15);
15329  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15330  rs1 += rs1_0;
15331  etiss_uint64 rd = 0;
15332  static BitArrayRange R_rd_0 (11,7);
15333  etiss_uint64 rd_0 = R_rd_0.read(ba);
15334  rd += rd_0;
15335  etiss_uint64 rm = 0;
15336  static BitArrayRange R_rm_0 (14,12);
15337  etiss_uint64 rm_0 = R_rm_0.read(ba);
15338  rm += rm_0;
15339  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15340  partInit.getAffectedRegisters().add(reg_name[rd],64);
15341  partInit.getAffectedRegisters().add("instructionPointer",64);
15342  partInit.code() = std::string("//fcvt.lu.d\n")+
15343  "etiss_uint32 temp = 0;\n"
15344  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15345  #if RISCV64_Pipeline1
15346  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15347  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15348  "etiss_uint32 num_stages = 4;\n"
15349  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15350  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15351  #endif
15352  #if RISCV64_Pipeline2
15353  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15354  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15355  "etiss_uint32 num_stages = 4;\n"
15356  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15357  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15358  #endif
15359 
15360  "etiss_uint32 flags = 0;\n"
15361 
15362 "etiss_int64 cast_0 = fcvt_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n"
15363 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15364 "{\n"
15365  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15366 "}\n"
15367 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15368 #if RISCV64_DEBUG_CALL
15369 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15370 #endif
15371 "flags = fget_flags();\n"
15372 #if RISCV64_DEBUG_CALL
15373 "printf(\"flags = %#x\\n\",flags); \n"
15374 #endif
15375 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
15376 #if RISCV64_DEBUG_CALL
15377 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
15378 #endif
15379 
15380  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15381 
15382 ;
15383 return true;
15384 },
15385 0,
15386 nullptr
15387 );
15388 //-------------------------------------------------------------------------------------------------------------------
15389 static InstructionDefinition fcvt_d_w_rd_rs1(
15390  ISA32_RISCV64,
15391  "fcvt.d.w",
15392  (uint32_t)0xd2000053,
15393  (uint32_t) 0xfff0007f,
15394  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15395  {
15396  etiss_uint64 rs1 = 0;
15397  static BitArrayRange R_rs1_0 (19,15);
15398  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15399  rs1 += rs1_0;
15400  etiss_uint64 rd = 0;
15401  static BitArrayRange R_rd_0 (11,7);
15402  etiss_uint64 rd_0 = R_rd_0.read(ba);
15403  rd += rd_0;
15404  etiss_uint64 rm = 0;
15405  static BitArrayRange R_rm_0 (14,12);
15406  etiss_uint64 rm_0 = R_rm_0.read(ba);
15407  rm += rm_0;
15408  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15409  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15410  partInit.getAffectedRegisters().add(reg_name[rd],64);
15411  partInit.getAffectedRegisters().add("instructionPointer",64);
15412  partInit.code() = std::string("//fcvt.d.w\n")+
15413  "etiss_uint32 temp = 0;\n"
15414  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15415  #if RISCV64_Pipeline1
15416  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15417  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15418  "etiss_uint32 num_stages = 4;\n"
15419  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15420  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15421  #endif
15422  #if RISCV64_Pipeline2
15423  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15424  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15425  "etiss_uint32 num_stages = 4;\n"
15426  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15427  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15428  #endif
15429 
15430  "etiss_uint64 res = 0;\n"
15431  "etiss_int64 upper = 0;\n"
15432 
15433 "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
15434 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15435 "{\n"
15436  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15437 "}\n"
15438 "res = fcvt_32_64((etiss_int64)cast_0, (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n"
15439 #if RISCV64_DEBUG_CALL
15440 "printf(\"res = %#lx\\n\",res); \n"
15441 #endif
15442 "if(64 == 64)\n"
15443 "{\n"
15444  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
15445  #if RISCV64_DEBUG_CALL
15446  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15447  #endif
15448 "}\n"
15449 
15450 "else\n"
15451 "{\n"
15452  "upper = - 1;\n"
15453  #if RISCV64_DEBUG_CALL
15454  "printf(\"upper = %#lx\\n\",upper); \n"
15455  #endif
15456  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
15457  #if RISCV64_DEBUG_CALL
15458  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15459  #endif
15460 "}\n"
15461 
15462  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15463 
15464 ;
15465 return true;
15466 },
15467 0,
15468 nullptr
15469 );
15470 //-------------------------------------------------------------------------------------------------------------------
15471 static InstructionDefinition fcvt_d_wu_rd_rs1(
15472  ISA32_RISCV64,
15473  "fcvt.d.wu",
15474  (uint32_t)0xd2100053,
15475  (uint32_t) 0xfff0007f,
15476  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15477  {
15478  etiss_uint64 rs1 = 0;
15479  static BitArrayRange R_rs1_0 (19,15);
15480  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15481  rs1 += rs1_0;
15482  etiss_uint64 rd = 0;
15483  static BitArrayRange R_rd_0 (11,7);
15484  etiss_uint64 rd_0 = R_rd_0.read(ba);
15485  rd += rd_0;
15486  etiss_uint64 rm = 0;
15487  static BitArrayRange R_rm_0 (14,12);
15488  etiss_uint64 rm_0 = R_rm_0.read(ba);
15489  rm += rm_0;
15490  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15491  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15492  partInit.getAffectedRegisters().add(reg_name[rd],64);
15493  partInit.getAffectedRegisters().add("instructionPointer",64);
15494  partInit.code() = std::string("//fcvt.d.wu\n")+
15495  "etiss_uint32 temp = 0;\n"
15496  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15497  #if RISCV64_Pipeline1
15498  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15499  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15500  "etiss_uint32 num_stages = 4;\n"
15501  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15502  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15503  #endif
15504  #if RISCV64_Pipeline2
15505  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15506  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15507  "etiss_uint32 num_stages = 4;\n"
15508  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15509  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15510  #endif
15511 
15512  "etiss_uint64 res = 0;\n"
15513  "etiss_int64 upper = 0;\n"
15514 
15515 "res = fcvt_32_64((etiss_uint64)(*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n"
15516 #if RISCV64_DEBUG_CALL
15517 "printf(\"res = %#lx\\n\",res); \n"
15518 #endif
15519 "if(64 == 64)\n"
15520 "{\n"
15521  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
15522  #if RISCV64_DEBUG_CALL
15523  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15524  #endif
15525 "}\n"
15526 
15527 "else\n"
15528 "{\n"
15529  "upper = - 1;\n"
15530  #if RISCV64_DEBUG_CALL
15531  "printf(\"upper = %#lx\\n\",upper); \n"
15532  #endif
15533  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
15534  #if RISCV64_DEBUG_CALL
15535  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15536  #endif
15537 "}\n"
15538 
15539  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15540 
15541 ;
15542 return true;
15543 },
15544 0,
15545 nullptr
15546 );
15547 //-------------------------------------------------------------------------------------------------------------------
15548 static InstructionDefinition fcvt_d_l_rd_rs1(
15549  ISA32_RISCV64,
15550  "fcvt.d.l",
15551  (uint32_t)0xd2200053,
15552  (uint32_t) 0xfff0007f,
15553  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15554  {
15555  etiss_uint64 rs1 = 0;
15556  static BitArrayRange R_rs1_0 (19,15);
15557  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15558  rs1 += rs1_0;
15559  etiss_uint64 rd = 0;
15560  static BitArrayRange R_rd_0 (11,7);
15561  etiss_uint64 rd_0 = R_rd_0.read(ba);
15562  rd += rd_0;
15563  etiss_uint64 rm = 0;
15564  static BitArrayRange R_rm_0 (14,12);
15565  etiss_uint64 rm_0 = R_rm_0.read(ba);
15566  rm += rm_0;
15567  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15568  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15569  partInit.getAffectedRegisters().add(reg_name[rd],64);
15570  partInit.getAffectedRegisters().add("instructionPointer",64);
15571  partInit.code() = std::string("//fcvt.d.l\n")+
15572  "etiss_uint32 temp = 0;\n"
15573  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15574  #if RISCV64_Pipeline1
15575  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15576  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15577  "etiss_uint32 num_stages = 4;\n"
15578  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15579  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15580  #endif
15581  #if RISCV64_Pipeline2
15582  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15583  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15584  "etiss_uint32 num_stages = 4;\n"
15585  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15586  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15587  #endif
15588 
15589  "etiss_uint64 res = 0;\n"
15590  "etiss_int64 upper = 0;\n"
15591 
15592 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
15593 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15594 "{\n"
15595  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15596 "}\n"
15597 "res = fcvt_d((etiss_int64)cast_0, (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n"
15598 #if RISCV64_DEBUG_CALL
15599 "printf(\"res = %#lx\\n\",res); \n"
15600 #endif
15601 "if(64 == 64)\n"
15602 "{\n"
15603  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
15604  #if RISCV64_DEBUG_CALL
15605  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15606  #endif
15607 "}\n"
15608 
15609 "else\n"
15610 "{\n"
15611  "upper = - 1;\n"
15612  #if RISCV64_DEBUG_CALL
15613  "printf(\"upper = %#lx\\n\",upper); \n"
15614  #endif
15615  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
15616  #if RISCV64_DEBUG_CALL
15617  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15618  #endif
15619 "}\n"
15620 
15621  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15622 
15623 ;
15624 return true;
15625 },
15626 0,
15627 nullptr
15628 );
15629 //-------------------------------------------------------------------------------------------------------------------
15630 static InstructionDefinition fcvt_d_lu_rd_rs1(
15631  ISA32_RISCV64,
15632  "fcvt.d.lu",
15633  (uint32_t)0xd2300053,
15634  (uint32_t) 0xfff0007f,
15635  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15636  {
15637  etiss_uint64 rs1 = 0;
15638  static BitArrayRange R_rs1_0 (19,15);
15639  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15640  rs1 += rs1_0;
15641  etiss_uint64 rd = 0;
15642  static BitArrayRange R_rd_0 (11,7);
15643  etiss_uint64 rd_0 = R_rd_0.read(ba);
15644  rd += rd_0;
15645  etiss_uint64 rm = 0;
15646  static BitArrayRange R_rm_0 (14,12);
15647  etiss_uint64 rm_0 = R_rm_0.read(ba);
15648  rm += rm_0;
15649  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15650  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15651  partInit.getAffectedRegisters().add(reg_name[rd],64);
15652  partInit.getAffectedRegisters().add("instructionPointer",64);
15653  partInit.code() = std::string("//fcvt.d.lu\n")+
15654  "etiss_uint32 temp = 0;\n"
15655  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15656  #if RISCV64_Pipeline1
15657  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15658  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15659  "etiss_uint32 num_stages = 4;\n"
15660  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15661  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15662  #endif
15663  #if RISCV64_Pipeline2
15664  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15665  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15666  "etiss_uint32 num_stages = 4;\n"
15667  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15668  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15669  #endif
15670 
15671  "etiss_uint64 res = 0;\n"
15672  "etiss_int64 upper = 0;\n"
15673 
15674 "res = fcvt_d((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "], (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n"
15675 #if RISCV64_DEBUG_CALL
15676 "printf(\"res = %#lx\\n\",res); \n"
15677 #endif
15678 "if(64 == 64)\n"
15679 "{\n"
15680  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
15681  #if RISCV64_DEBUG_CALL
15682  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15683  #endif
15684 "}\n"
15685 
15686 "else\n"
15687 "{\n"
15688  "upper = - 1;\n"
15689  #if RISCV64_DEBUG_CALL
15690  "printf(\"upper = %#lx\\n\",upper); \n"
15691  #endif
15692  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
15693  #if RISCV64_DEBUG_CALL
15694  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15695  #endif
15696 "}\n"
15697 
15698  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15699 
15700 ;
15701 return true;
15702 },
15703 0,
15704 nullptr
15705 );
15706 //-------------------------------------------------------------------------------------------------------------------
15707 static InstructionDefinition fmv_d_x_rd_rs1(
15708  ISA32_RISCV64,
15709  "fmv.d.x",
15710  (uint32_t)0xf2000053,
15711  (uint32_t) 0xfff0707f,
15712  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15713  {
15714  etiss_uint64 rs1 = 0;
15715  static BitArrayRange R_rs1_0 (19,15);
15716  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15717  rs1 += rs1_0;
15718  etiss_uint64 rd = 0;
15719  static BitArrayRange R_rd_0 (11,7);
15720  etiss_uint64 rd_0 = R_rd_0.read(ba);
15721  rd += rd_0;
15722  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15723  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15724  partInit.getAffectedRegisters().add(reg_name[rd],64);
15725  partInit.getAffectedRegisters().add("instructionPointer",64);
15726  partInit.code() = std::string("//fmv.d.x\n")+
15727  "etiss_uint32 temp = 0;\n"
15728  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15729  #if RISCV64_Pipeline1
15730  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15731  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15732  "etiss_uint32 num_stages = 4;\n"
15733  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15734  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15735  #endif
15736  #if RISCV64_Pipeline2
15737  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15738  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15739  "etiss_uint32 num_stages = 4;\n"
15740  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15741  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15742  #endif
15743 
15744 
15745 "((RISCV64*)cpu)->F[" + toString(rd) + "] = (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
15746 #if RISCV64_DEBUG_CALL
15747 "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15748 #endif
15749 
15750  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15751 
15752 ;
15753 return true;
15754 },
15755 0,
15756 nullptr
15757 );
15758 //-------------------------------------------------------------------------------------------------------------------
15759 static InstructionDefinition c_addi4spn_rd_imm(
15760  ISA16_RISCV64,
15761  "c.addi4spn",
15762  (uint16_t)0x0,
15763  (uint16_t) 0xe003,
15764  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15765  {
15766  etiss_uint64 rd = 0;
15767  static BitArrayRange R_rd_0 (4,2);
15768  etiss_uint64 rd_0 = R_rd_0.read(ba);
15769  rd += rd_0;
15770  etiss_uint64 imm = 0;
15771  static BitArrayRange R_imm_4 (12,11);
15772  etiss_uint64 imm_4 = R_imm_4.read(ba);
15773  imm += imm_4<<4;
15774  static BitArrayRange R_imm_6 (10,7);
15775  etiss_uint64 imm_6 = R_imm_6.read(ba);
15776  imm += imm_6<<6;
15777  static BitArrayRange R_imm_2 (6,6);
15778  etiss_uint64 imm_2 = R_imm_2.read(ba);
15779  imm += imm_2<<2;
15780  static BitArrayRange R_imm_3 (5,5);
15781  etiss_uint64 imm_3 = R_imm_3.read(ba);
15782  imm += imm_3<<3;
15783  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15784  partInit.getRegisterDependencies().add(reg_name[2],64);
15785  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
15786  partInit.getAffectedRegisters().add("instructionPointer",64);
15787  partInit.code() = std::string("//c.addi4spn\n")+
15788  "etiss_uint32 exception = 0;\n"
15789  "etiss_uint32 temp = 0;\n"
15790  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15791  #if RISCV64_Pipeline1
15792  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15793  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15794  "etiss_uint32 num_stages = 4;\n"
15795  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15796  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15797  #endif
15798  #if RISCV64_Pipeline2
15799  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15800  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15801  "etiss_uint32 num_stages = 4;\n"
15802  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15803  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15804  #endif
15805 
15806 
15807 "if(" + toString(imm) + " == 0)\n"
15808 "{\n"
15809  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
15810 "}\n"
15811 
15812 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = *((RISCV64*)cpu)->X[2] + " + toString(imm) + ";\n"
15813 #if RISCV64_DEBUG_CALL
15814 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
15815 #endif
15816 
15817  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
15818 
15819  "return exception;\n"
15820 ;
15821 return true;
15822 },
15823 0,
15824 nullptr
15825 );
15826 //-------------------------------------------------------------------------------------------------------------------
15827 static InstructionDefinition c_addi_rs1_imm(
15828  ISA16_RISCV64,
15829  "c.addi",
15830  (uint16_t)0x1,
15831  (uint16_t) 0xe003,
15832  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15833  {
15834  etiss_uint64 rs1 = 0;
15835  static BitArrayRange R_rs1_0 (11,7);
15836  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15837  rs1 += rs1_0;
15838  etiss_int64 imm = 0;
15839  static BitArrayRange R_imm_5 (12,12);
15840  etiss_int64 imm_5 = R_imm_5.read(ba);
15841  imm += imm_5<<5;
15842  static BitArrayRange R_imm_0 (6,2);
15843  etiss_int64 imm_0 = R_imm_0.read(ba);
15844  imm += imm_0;
15845  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15846  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15847  partInit.getAffectedRegisters().add(reg_name[rs1],64);
15848  partInit.getAffectedRegisters().add("instructionPointer",64);
15849  partInit.code() = std::string("//c.addi\n")+
15850  "etiss_uint32 temp = 0;\n"
15851  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15852  #if RISCV64_Pipeline1
15853  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15854  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15855  "etiss_uint32 num_stages = 4;\n"
15856  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15857  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15858  #endif
15859  #if RISCV64_Pipeline2
15860  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15861  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15862  "etiss_uint32 num_stages = 4;\n"
15863  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15864  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15865  #endif
15866 
15867  "etiss_int64 imm_extended = 0;\n"
15868 
15869 "if((" + toString(imm) + " & 0x20)>>5 == 0)\n"
15870 "{\n"
15871  "imm_extended = 0;\n"
15872  #if RISCV64_DEBUG_CALL
15873  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
15874  #endif
15875 "}\n"
15876 
15877 "else\n"
15878 "{\n"
15879  "imm_extended = 4294967295;\n"
15880  #if RISCV64_DEBUG_CALL
15881  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
15882  #endif
15883  "imm_extended = (imm_extended << 32);\n"
15884  #if RISCV64_DEBUG_CALL
15885  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
15886  #endif
15887  "imm_extended = imm_extended + 4294967232;\n"
15888  #if RISCV64_DEBUG_CALL
15889  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
15890  #endif
15891 "}\n"
15892 "imm_extended = imm_extended + " + toString(imm) + ";\n"
15893 #if RISCV64_DEBUG_CALL
15894 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
15895 #endif
15896 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
15897 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15898 "{\n"
15899  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15900 "}\n"
15901 "*((RISCV64*)cpu)->X[" + toString(rs1) + "] = (etiss_int64)cast_0 + imm_extended;\n"
15902 #if RISCV64_DEBUG_CALL
15903 "printf(\"*((RISCV64*)cpu)->X[" + toString(rs1) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rs1) + "]); \n"
15904 #endif
15905 
15906  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
15907 
15908 ;
15909 return true;
15910 },
15911 0,
15912 nullptr
15913 );
15914 //-------------------------------------------------------------------------------------------------------------------
15915 static InstructionDefinition c_nop_(
15916  ISA16_RISCV64,
15917  "c.nop",
15918  (uint16_t)0x1,
15919  (uint16_t) 0xffff,
15920  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15921  {
15922  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15923  partInit.getAffectedRegisters().add("instructionPointer",64);
15924  partInit.code() = std::string("//c.nop\n")+
15925  "etiss_uint32 temp = 0;\n"
15926  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15927  #if RISCV64_Pipeline1
15928  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15929  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15930  "etiss_uint32 num_stages = 4;\n"
15931  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15932  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15933  #endif
15934  #if RISCV64_Pipeline2
15935  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15936  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15937  "etiss_uint32 num_stages = 4;\n"
15938  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15939  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15940  #endif
15941 
15942 
15943 
15944  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
15945 
15946 ;
15947 return true;
15948 },
15949 0,
15950 nullptr
15951 );
15952 //-------------------------------------------------------------------------------------------------------------------
15953 static InstructionDefinition dii_(
15954  ISA16_RISCV64,
15955  "dii",
15956  (uint16_t)0x0,
15957  (uint16_t) 0xffff,
15958  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15959  {
15960  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15961  partInit.getAffectedRegisters().add("instructionPointer",64);
15962  partInit.code() = std::string("//dii\n")+
15963  "etiss_uint32 exception = 0;\n"
15964  "etiss_uint32 temp = 0;\n"
15965  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15966  #if RISCV64_Pipeline1
15967  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15968  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15969  "etiss_uint32 num_stages = 4;\n"
15970  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15971  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15972  #endif
15973  #if RISCV64_Pipeline2
15974  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15975  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15976  "etiss_uint32 num_stages = 4;\n"
15977  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15978  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15979  #endif
15980 
15981 
15982 "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
15983 
15984  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
15985 
15986  "return exception;\n"
15987 ;
15988 return true;
15989 },
15990 0,
15991 nullptr
15992 );
15993 //-------------------------------------------------------------------------------------------------------------------
15994 static InstructionDefinition c_slli_rs1_shamt(
15995  ISA16_RISCV64,
15996  "c.slli",
15997  (uint16_t)0x2,
15998  (uint16_t) 0xe003,
15999  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16000  {
16001  etiss_uint64 rs1 = 0;
16002  static BitArrayRange R_rs1_0 (11,7);
16003  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16004  rs1 += rs1_0;
16005  etiss_uint64 shamt = 0;
16006  static BitArrayRange R_shamt_5 (12,12);
16007  etiss_uint64 shamt_5 = R_shamt_5.read(ba);
16008  shamt += shamt_5<<5;
16009  static BitArrayRange R_shamt_0 (6,2);
16010  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
16011  shamt += shamt_0;
16012  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16013  partInit.getRegisterDependencies().add(reg_name[rs1],64);
16014  partInit.getAffectedRegisters().add(reg_name[rs1],64);
16015  partInit.getAffectedRegisters().add("instructionPointer",64);
16016  partInit.code() = std::string("//c.slli\n")+
16017  "etiss_uint32 exception = 0;\n"
16018  "etiss_uint32 temp = 0;\n"
16019  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16020  #if RISCV64_Pipeline1
16021  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16022  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16023  "etiss_uint32 num_stages = 4;\n"
16024  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16025  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16026  #endif
16027  #if RISCV64_Pipeline2
16028  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16029  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16030  "etiss_uint32 num_stages = 4;\n"
16031  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16032  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16033  #endif
16034 
16035 
16036 "if(" + toString(rs1) + " == 0)\n"
16037 "{\n"
16038  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
16039 "}\n"
16040 
16041 "*((RISCV64*)cpu)->X[" + toString(rs1) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] << " + toString(shamt) + ");\n"
16042 #if RISCV64_DEBUG_CALL
16043 "printf(\"*((RISCV64*)cpu)->X[" + toString(rs1) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rs1) + "]); \n"
16044 #endif
16045 
16046  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16047 
16048  "return exception;\n"
16049 ;
16050 return true;
16051 },
16052 0,
16053 nullptr
16054 );
16055 //-------------------------------------------------------------------------------------------------------------------
16056 static InstructionDefinition c_lw_8_rd_uimm_8_rs1_(
16057  ISA16_RISCV64,
16058  "c.lw",
16059  (uint16_t)0x4000,
16060  (uint16_t) 0xe003,
16061  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16062  {
16063  etiss_uint64 rs1 = 0;
16064  static BitArrayRange R_rs1_0 (9,7);
16065  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16066  rs1 += rs1_0;
16067  etiss_uint64 uimm = 0;
16068  static BitArrayRange R_uimm_3 (12,10);
16069  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
16070  uimm += uimm_3<<3;
16071  static BitArrayRange R_uimm_2 (6,6);
16072  etiss_uint64 uimm_2 = R_uimm_2.read(ba);
16073  uimm += uimm_2<<2;
16074  static BitArrayRange R_uimm_6 (5,5);
16075  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16076  uimm += uimm_6<<6;
16077  etiss_uint64 rd = 0;
16078  static BitArrayRange R_rd_0 (4,2);
16079  etiss_uint64 rd_0 = R_rd_0.read(ba);
16080  rd += rd_0;
16081  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16082  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
16083  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
16084  partInit.getAffectedRegisters().add("instructionPointer",64);
16085  partInit.code() = std::string("//c.lw\n")+
16086  "etiss_uint32 exception = 0;\n"
16087  "etiss_uint32 temp = 0;\n"
16088  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16089  #if RISCV64_Pipeline1
16090  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16091  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16092  "etiss_uint32 num_stages = 4;\n"
16093  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16094  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16095  #endif
16096  #if RISCV64_Pipeline2
16097  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16098  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16099  "etiss_uint32 num_stages = 4;\n"
16100  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16101  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16102  #endif
16103 
16104  "etiss_uint64 offs = 0;\n"
16105 
16106 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
16107 #if RISCV64_DEBUG_CALL
16108 "printf(\"offs = %#lx\\n\",offs); \n"
16109 #endif
16110  "etiss_uint32 MEM_offs;\n"
16111 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16112 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
16113 "etiss_int32 cast_0 = MEM_offs; \n"
16114 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
16115 "{\n"
16116  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
16117 "}\n"
16118 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = (etiss_int64)cast_0;\n"
16119 #if RISCV64_DEBUG_CALL
16120 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
16121 #endif
16122 
16123  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16124 
16125  "return exception;\n"
16126 ;
16127 return true;
16128 },
16129 0,
16130 nullptr
16131 );
16132 //-------------------------------------------------------------------------------------------------------------------
16133 static InstructionDefinition c_li_rd_imm(
16134  ISA16_RISCV64,
16135  "c.li",
16136  (uint16_t)0x4001,
16137  (uint16_t) 0xe003,
16138  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16139  {
16140  etiss_uint64 rd = 0;
16141  static BitArrayRange R_rd_0 (11,7);
16142  etiss_uint64 rd_0 = R_rd_0.read(ba);
16143  rd += rd_0;
16144  etiss_int64 imm = 0;
16145  static BitArrayRange R_imm_5 (12,12);
16146  etiss_int64 imm_5 = R_imm_5.read(ba);
16147  imm += imm_5<<5;
16148  static BitArrayRange R_imm_0 (6,2);
16149  etiss_int64 imm_0 = R_imm_0.read(ba);
16150  imm += imm_0;
16151  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16152  partInit.getAffectedRegisters().add(reg_name[rd],64);
16153  partInit.getAffectedRegisters().add("instructionPointer",64);
16154  partInit.code() = std::string("//c.li\n")+
16155  "etiss_uint32 exception = 0;\n"
16156  "etiss_uint32 temp = 0;\n"
16157  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16158  #if RISCV64_Pipeline1
16159  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16160  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16161  "etiss_uint32 num_stages = 4;\n"
16162  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16163  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16164  #endif
16165  #if RISCV64_Pipeline2
16166  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16167  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16168  "etiss_uint32 num_stages = 4;\n"
16169  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16170  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16171  #endif
16172 
16173  "etiss_int64 imm_extended = 0;\n"
16174 
16175 "if((" + toString(imm) + " & 0x20)>>5 == 0)\n"
16176 "{\n"
16177  "imm_extended = 0;\n"
16178  #if RISCV64_DEBUG_CALL
16179  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16180  #endif
16181 "}\n"
16182 
16183 "else\n"
16184 "{\n"
16185  "imm_extended = 4294967295;\n"
16186  #if RISCV64_DEBUG_CALL
16187  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16188  #endif
16189  "imm_extended = (imm_extended << 32);\n"
16190  #if RISCV64_DEBUG_CALL
16191  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16192  #endif
16193  "imm_extended = imm_extended + 4294967232;\n"
16194  #if RISCV64_DEBUG_CALL
16195  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16196  #endif
16197 "}\n"
16198 "imm_extended = imm_extended + " + toString(imm) + ";\n"
16199 #if RISCV64_DEBUG_CALL
16200 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16201 #endif
16202 "if(" + toString(rd) + " == 0)\n"
16203 "{\n"
16204  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
16205 "}\n"
16206 
16207 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = imm_extended;\n"
16208 #if RISCV64_DEBUG_CALL
16209 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
16210 #endif
16211 
16212  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16213 
16214  "return exception;\n"
16215 ;
16216 return true;
16217 },
16218 0,
16219 nullptr
16220 );
16221 //-------------------------------------------------------------------------------------------------------------------
16222 static InstructionDefinition c_lwsp_rd_sp_uimm(
16223  ISA16_RISCV64,
16224  "c.lwsp",
16225  (uint16_t)0x4002,
16226  (uint16_t) 0xe003,
16227  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16228  {
16229  etiss_uint64 uimm = 0;
16230  static BitArrayRange R_uimm_5 (12,12);
16231  etiss_uint64 uimm_5 = R_uimm_5.read(ba);
16232  uimm += uimm_5<<5;
16233  static BitArrayRange R_uimm_2 (6,4);
16234  etiss_uint64 uimm_2 = R_uimm_2.read(ba);
16235  uimm += uimm_2<<2;
16236  static BitArrayRange R_uimm_6 (3,2);
16237  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16238  uimm += uimm_6<<6;
16239  etiss_uint64 rd = 0;
16240  static BitArrayRange R_rd_0 (11,7);
16241  etiss_uint64 rd_0 = R_rd_0.read(ba);
16242  rd += rd_0;
16243  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16244  partInit.getRegisterDependencies().add(reg_name[2],64);
16245  partInit.getAffectedRegisters().add(reg_name[rd],64);
16246  partInit.getAffectedRegisters().add("instructionPointer",64);
16247  partInit.code() = std::string("//c.lwsp\n")+
16248  "etiss_uint32 exception = 0;\n"
16249  "etiss_uint32 temp = 0;\n"
16250  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16251  #if RISCV64_Pipeline1
16252  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16253  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16254  "etiss_uint32 num_stages = 4;\n"
16255  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16256  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16257  #endif
16258  #if RISCV64_Pipeline2
16259  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16260  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16261  "etiss_uint32 num_stages = 4;\n"
16262  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16263  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16264  #endif
16265 
16266  "etiss_uint64 offs = 0;\n"
16267 
16268 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
16269 #if RISCV64_DEBUG_CALL
16270 "printf(\"offs = %#lx\\n\",offs); \n"
16271 #endif
16272  "etiss_uint32 MEM_offs;\n"
16273 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16274 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
16275 "etiss_int32 cast_0 = MEM_offs; \n"
16276 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
16277 "{\n"
16278  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
16279 "}\n"
16280 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
16281 #if RISCV64_DEBUG_CALL
16282 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
16283 #endif
16284 
16285  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16286 
16287  "return exception;\n"
16288 ;
16289 return true;
16290 },
16291 0,
16292 nullptr
16293 );
16294 //-------------------------------------------------------------------------------------------------------------------
16295 static InstructionDefinition c_sw_8_rs2_uimm_8_rs1_(
16296  ISA16_RISCV64,
16297  "c.sw",
16298  (uint16_t)0xc000,
16299  (uint16_t) 0xe003,
16300  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16301  {
16302  etiss_uint64 rs2 = 0;
16303  static BitArrayRange R_rs2_0 (4,2);
16304  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
16305  rs2 += rs2_0;
16306  etiss_uint64 rs1 = 0;
16307  static BitArrayRange R_rs1_0 (9,7);
16308  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16309  rs1 += rs1_0;
16310  etiss_uint64 uimm = 0;
16311  static BitArrayRange R_uimm_3 (12,10);
16312  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
16313  uimm += uimm_3<<3;
16314  static BitArrayRange R_uimm_2 (6,6);
16315  etiss_uint64 uimm_2 = R_uimm_2.read(ba);
16316  uimm += uimm_2<<2;
16317  static BitArrayRange R_uimm_6 (5,5);
16318  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16319  uimm += uimm_6<<6;
16320  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16321  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
16322  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
16323  partInit.getAffectedRegisters().add("instructionPointer",64);
16324  partInit.code() = std::string("//c.sw\n")+
16325  "etiss_uint32 exception = 0;\n"
16326  "etiss_uint32 temp = 0;\n"
16327  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16328  #if RISCV64_Pipeline1
16329  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16330  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16331  "etiss_uint32 num_stages = 4;\n"
16332  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16333  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16334  #endif
16335  #if RISCV64_Pipeline2
16336  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16337  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16338  "etiss_uint32 num_stages = 4;\n"
16339  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16340  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16341  #endif
16342 
16343  "etiss_uint64 offs = 0;\n"
16344 
16345 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
16346 #if RISCV64_DEBUG_CALL
16347 "printf(\"offs = %#lx\\n\",offs); \n"
16348 #endif
16349  "etiss_uint32 MEM_offs;\n"
16350 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16351 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8];\n"
16352 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
16353 #if RISCV64_DEBUG_CALL
16354 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
16355 #endif
16356 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
16357 "{\n"
16358  "((RISCV64*)cpu)->RES = 0;\n"
16359  #if RISCV64_DEBUG_CALL
16360  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
16361  #endif
16362 "}\n"
16363 
16364 
16365  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16366 
16367  "return exception;\n"
16368 ;
16369 return true;
16370 },
16371 0,
16372 nullptr
16373 );
16374 //-------------------------------------------------------------------------------------------------------------------
16375 static InstructionDefinition c_beqz_8_rs1_imm(
16376  ISA16_RISCV64,
16377  "c.beqz",
16378  (uint16_t)0xc001,
16379  (uint16_t) 0xe003,
16380  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16381  {
16382  etiss_uint64 rs1 = 0;
16383  static BitArrayRange R_rs1_0 (9,7);
16384  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16385  rs1 += rs1_0;
16386  etiss_int64 imm = 0;
16387  static BitArrayRange R_imm_8 (12,12);
16388  etiss_int64 imm_8 = R_imm_8.read(ba);
16389  imm += imm_8<<8;
16390  static BitArrayRange R_imm_3 (11,10);
16391  etiss_int64 imm_3 = R_imm_3.read(ba);
16392  imm += imm_3<<3;
16393  static BitArrayRange R_imm_6 (6,5);
16394  etiss_int64 imm_6 = R_imm_6.read(ba);
16395  imm += imm_6<<6;
16396  static BitArrayRange R_imm_1 (4,3);
16397  etiss_int64 imm_1 = R_imm_1.read(ba);
16398  imm += imm_1<<1;
16399  static BitArrayRange R_imm_5 (2,2);
16400  etiss_int64 imm_5 = R_imm_5.read(ba);
16401  imm += imm_5<<5;
16402  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16403  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
16404  partInit.getAffectedRegisters().add("instructionPointer",64);
16405  partInit.code() = std::string("//c.beqz\n")+
16406  "etiss_uint32 temp = 0;\n"
16407  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16408  #if RISCV64_Pipeline1
16409  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16410  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16411  "etiss_uint32 num_stages = 4;\n"
16412  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16413  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16414  #endif
16415  #if RISCV64_Pipeline2
16416  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16417  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16418  "etiss_uint32 num_stages = 4;\n"
16419  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16420  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16421  #endif
16422 
16423  "etiss_int64 imm_extended = 0;\n"
16424  "etiss_int64 choose1 = 0;\n"
16425 
16426 "if((" + toString(imm) + " & 0x100)>>8 == 0)\n"
16427 "{\n"
16428  "imm_extended = 0;\n"
16429  #if RISCV64_DEBUG_CALL
16430  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16431  #endif
16432 "}\n"
16433 
16434 "else\n"
16435 "{\n"
16436  "imm_extended = 4294967295;\n"
16437  #if RISCV64_DEBUG_CALL
16438  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16439  #endif
16440  "imm_extended = (imm_extended << 32);\n"
16441  #if RISCV64_DEBUG_CALL
16442  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16443  #endif
16444  "imm_extended = imm_extended + 4294966784;\n"
16445  #if RISCV64_DEBUG_CALL
16446  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16447  #endif
16448 "}\n"
16449 "imm_extended = imm_extended + " + toString(imm) + ";\n"
16450 #if RISCV64_DEBUG_CALL
16451 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16452 #endif
16453 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] == 0)\n"
16454 "{\n"
16455  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
16456  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
16457  "{\n"
16458  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
16459  "}\n"
16460  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
16461  #if RISCV64_DEBUG_CALL
16462  "printf(\"choose1 = %#lx\\n\",choose1); \n"
16463  #endif
16464 // Explicit assignment to PC
16465 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16466 "}\n"
16467 
16468 "else\n"
16469 "{\n"
16470  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 2;\n"
16471  #if RISCV64_DEBUG_CALL
16472  "printf(\"choose1 = %#lx\\n\",choose1); \n"
16473  #endif
16474 "}\n"
16475 "cpu->instructionPointer = choose1;\n"
16476 #if RISCV64_DEBUG_CALL
16477 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
16478 #endif
16479 
16480  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
16481 
16482  "return 0;\n"
16483 ;
16484 return true;
16485 },
16486 0,
16487 nullptr
16488 );
16489 //-------------------------------------------------------------------------------------------------------------------
16490 static InstructionDefinition c_swsp_rs2_uimm_sp_(
16491  ISA16_RISCV64,
16492  "c.swsp",
16493  (uint16_t)0xc002,
16494  (uint16_t) 0xe003,
16495  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16496  {
16497  etiss_uint64 rs2 = 0;
16498  static BitArrayRange R_rs2_0 (6,2);
16499  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
16500  rs2 += rs2_0;
16501  etiss_uint64 uimm = 0;
16502  static BitArrayRange R_uimm_2 (12,9);
16503  etiss_uint64 uimm_2 = R_uimm_2.read(ba);
16504  uimm += uimm_2<<2;
16505  static BitArrayRange R_uimm_6 (8,7);
16506  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16507  uimm += uimm_6<<6;
16508  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16509  partInit.getRegisterDependencies().add(reg_name[rs2],64);
16510  partInit.getRegisterDependencies().add(reg_name[2],64);
16511  partInit.getAffectedRegisters().add("instructionPointer",64);
16512  partInit.code() = std::string("//c.swsp\n")+
16513  "etiss_uint32 exception = 0;\n"
16514  "etiss_uint32 temp = 0;\n"
16515  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16516  #if RISCV64_Pipeline1
16517  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16518  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16519  "etiss_uint32 num_stages = 4;\n"
16520  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16521  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16522  #endif
16523  #if RISCV64_Pipeline2
16524  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16525  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16526  "etiss_uint32 num_stages = 4;\n"
16527  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16528  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16529  #endif
16530 
16531  "etiss_uint64 offs = 0;\n"
16532 
16533 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
16534 #if RISCV64_DEBUG_CALL
16535 "printf(\"offs = %#lx\\n\",offs); \n"
16536 #endif
16537  "etiss_uint32 MEM_offs;\n"
16538 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16539 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
16540 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
16541 #if RISCV64_DEBUG_CALL
16542 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
16543 #endif
16544 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
16545 "{\n"
16546  "((RISCV64*)cpu)->RES = 0;\n"
16547  #if RISCV64_DEBUG_CALL
16548  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
16549  #endif
16550 "}\n"
16551 
16552 
16553  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16554 
16555  "return exception;\n"
16556 ;
16557 return true;
16558 },
16559 0,
16560 nullptr
16561 );
16562 //-------------------------------------------------------------------------------------------------------------------
16563 static InstructionDefinition c_addiw_rs1_imm(
16564  ISA16_RISCV64,
16565  "c.addiw",
16566  (uint16_t)0x2001,
16567  (uint16_t) 0xe003,
16568  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16569  {
16570  etiss_uint64 rs1 = 0;
16571  static BitArrayRange R_rs1_0 (11,7);
16572  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16573  rs1 += rs1_0;
16574  etiss_int64 imm = 0;
16575  static BitArrayRange R_imm_5 (12,12);
16576  etiss_int64 imm_5 = R_imm_5.read(ba);
16577  imm += imm_5<<5;
16578  static BitArrayRange R_imm_0 (6,2);
16579  etiss_int64 imm_0 = R_imm_0.read(ba);
16580  imm += imm_0;
16581  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16582  partInit.getRegisterDependencies().add(reg_name[rs1],64);
16583  partInit.getAffectedRegisters().add(reg_name[rs1],64);
16584  partInit.getAffectedRegisters().add("instructionPointer",64);
16585  partInit.code() = std::string("//c.addiw\n")+
16586  "etiss_uint32 temp = 0;\n"
16587  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16588  #if RISCV64_Pipeline1
16589  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16590  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16591  "etiss_uint32 num_stages = 4;\n"
16592  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16593  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16594  #endif
16595  #if RISCV64_Pipeline2
16596  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16597  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16598  "etiss_uint32 num_stages = 4;\n"
16599  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16600  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16601  #endif
16602 
16603  "etiss_int64 imm_extended = 0;\n"
16604  "etiss_int32 res = 0;\n"
16605 
16606 "if((" + toString(imm) + " & 0x20)>>5 == 0)\n"
16607 "{\n"
16608  "imm_extended = 0;\n"
16609  #if RISCV64_DEBUG_CALL
16610  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16611  #endif
16612 "}\n"
16613 
16614 "else\n"
16615 "{\n"
16616  "imm_extended = 4294967295;\n"
16617  #if RISCV64_DEBUG_CALL
16618  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16619  #endif
16620  "imm_extended = (imm_extended << 32);\n"
16621  #if RISCV64_DEBUG_CALL
16622  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16623  #endif
16624  "imm_extended = imm_extended + 4294967232;\n"
16625  #if RISCV64_DEBUG_CALL
16626  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16627  #endif
16628 "}\n"
16629 "imm_extended = imm_extended + " + toString(imm) + ";\n"
16630 #if RISCV64_DEBUG_CALL
16631 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16632 #endif
16633 "if(" + toString(rs1) + " != 0)\n"
16634 "{\n"
16635  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
16636  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
16637  "{\n"
16638  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
16639  "}\n"
16640  "res = (etiss_int32)cast_0 + imm_extended;\n"
16641  #if RISCV64_DEBUG_CALL
16642  "printf(\"res = %#x\\n\",res); \n"
16643  #endif
16644  "etiss_int32 cast_1 = res; \n"
16645  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
16646  "{\n"
16647  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
16648  "}\n"
16649  "*((RISCV64*)cpu)->X[" + toString(rs1) + "] = (etiss_int64)cast_1;\n"
16650  #if RISCV64_DEBUG_CALL
16651  "printf(\"*((RISCV64*)cpu)->X[" + toString(rs1) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rs1) + "]); \n"
16652  #endif
16653 "}\n"
16654 
16655 
16656  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16657 
16658 ;
16659 return true;
16660 },
16661 0,
16662 nullptr
16663 );
16664 //-------------------------------------------------------------------------------------------------------------------
16665 static InstructionDefinition c_fld_rd_uimm_8_rs1_(
16666  ISA16_RISCV64,
16667  "c.fld",
16668  (uint16_t)0x2000,
16669  (uint16_t) 0xe003,
16670  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16671  {
16672  etiss_uint64 rs1 = 0;
16673  static BitArrayRange R_rs1_0 (9,7);
16674  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16675  rs1 += rs1_0;
16676  etiss_uint64 uimm = 0;
16677  static BitArrayRange R_uimm_3 (12,10);
16678  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
16679  uimm += uimm_3<<3;
16680  static BitArrayRange R_uimm_6 (6,5);
16681  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16682  uimm += uimm_6<<6;
16683  etiss_uint64 rd = 0;
16684  static BitArrayRange R_rd_0 (4,2);
16685  etiss_uint64 rd_0 = R_rd_0.read(ba);
16686  rd += rd_0;
16687  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16688  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
16689  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
16690  partInit.getAffectedRegisters().add("instructionPointer",64);
16691  partInit.code() = std::string("//c.fld\n")+
16692  "etiss_uint32 exception = 0;\n"
16693  "etiss_uint32 temp = 0;\n"
16694  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16695  #if RISCV64_Pipeline1
16696  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16697  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16698  "etiss_uint32 num_stages = 4;\n"
16699  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16700  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16701  #endif
16702  #if RISCV64_Pipeline2
16703  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16704  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16705  "etiss_uint32 num_stages = 4;\n"
16706  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16707  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16708  #endif
16709 
16710  "etiss_uint64 offs = 0;\n"
16711  "etiss_uint64 res = 0;\n"
16712  "etiss_int64 upper = 0;\n"
16713 
16714 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
16715 #if RISCV64_DEBUG_CALL
16716 "printf(\"offs = %#lx\\n\",offs); \n"
16717 #endif
16718  "etiss_uint64 MEM_offs;\n"
16719 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16720 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
16721 "res = MEM_offs;\n"
16722 #if RISCV64_DEBUG_CALL
16723 "printf(\"res = %#lx\\n\",res); \n"
16724 #endif
16725 "if(64 == 64)\n"
16726 "{\n"
16727  "((RISCV64*)cpu)->F[" + toString(rd) + " + 8] = res;\n"
16728  #if RISCV64_DEBUG_CALL
16729  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + " + 8] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + " + 8]); \n"
16730  #endif
16731 "}\n"
16732 
16733 "else\n"
16734 "{\n"
16735  "upper = - 1;\n"
16736  #if RISCV64_DEBUG_CALL
16737  "printf(\"upper = %#lx\\n\",upper); \n"
16738  #endif
16739  "((RISCV64*)cpu)->F[" + toString(rd) + " + 8] = ((upper << 64) | res);\n"
16740  #if RISCV64_DEBUG_CALL
16741  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + " + 8] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + " + 8]); \n"
16742  #endif
16743 "}\n"
16744 
16745  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16746 
16747  "return exception;\n"
16748 ;
16749 return true;
16750 },
16751 0,
16752 nullptr
16753 );
16754 //-------------------------------------------------------------------------------------------------------------------
16755 static InstructionDefinition c_fldsp_rd_uimm_x2_(
16756  ISA16_RISCV64,
16757  "c.fldsp",
16758  (uint16_t)0x2002,
16759  (uint16_t) 0xe003,
16760  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16761  {
16762  etiss_uint64 uimm = 0;
16763  static BitArrayRange R_uimm_5 (12,12);
16764  etiss_uint64 uimm_5 = R_uimm_5.read(ba);
16765  uimm += uimm_5<<5;
16766  static BitArrayRange R_uimm_3 (6,5);
16767  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
16768  uimm += uimm_3<<3;
16769  static BitArrayRange R_uimm_6 (4,2);
16770  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16771  uimm += uimm_6<<6;
16772  etiss_uint64 rd = 0;
16773  static BitArrayRange R_rd_0 (11,7);
16774  etiss_uint64 rd_0 = R_rd_0.read(ba);
16775  rd += rd_0;
16776  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16777  partInit.getRegisterDependencies().add(reg_name[2],64);
16778  partInit.getAffectedRegisters().add(reg_name[rd],64);
16779  partInit.getAffectedRegisters().add("instructionPointer",64);
16780  partInit.code() = std::string("//c.fldsp\n")+
16781  "etiss_uint32 exception = 0;\n"
16782  "etiss_uint32 temp = 0;\n"
16783  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16784  #if RISCV64_Pipeline1
16785  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16786  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16787  "etiss_uint32 num_stages = 4;\n"
16788  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16789  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16790  #endif
16791  #if RISCV64_Pipeline2
16792  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16793  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16794  "etiss_uint32 num_stages = 4;\n"
16795  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16796  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16797  #endif
16798 
16799  "etiss_uint64 offs = 0;\n"
16800  "etiss_uint64 res = 0;\n"
16801  "etiss_int64 upper = 0;\n"
16802 
16803 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
16804 #if RISCV64_DEBUG_CALL
16805 "printf(\"offs = %#lx\\n\",offs); \n"
16806 #endif
16807  "etiss_uint64 MEM_offs;\n"
16808 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16809 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
16810 "res = MEM_offs;\n"
16811 #if RISCV64_DEBUG_CALL
16812 "printf(\"res = %#lx\\n\",res); \n"
16813 #endif
16814 "if(64 == 64)\n"
16815 "{\n"
16816  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
16817  #if RISCV64_DEBUG_CALL
16818  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
16819  #endif
16820 "}\n"
16821 
16822 "else\n"
16823 "{\n"
16824  "upper = - 1;\n"
16825  #if RISCV64_DEBUG_CALL
16826  "printf(\"upper = %#lx\\n\",upper); \n"
16827  #endif
16828  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | (etiss_uint64)res);\n"
16829  #if RISCV64_DEBUG_CALL
16830  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
16831  #endif
16832 "}\n"
16833 
16834  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16835 
16836  "return exception;\n"
16837 ;
16838 return true;
16839 },
16840 0,
16841 nullptr
16842 );
16843 //-------------------------------------------------------------------------------------------------------------------
16844 static InstructionDefinition c_lui_rd_imm(
16845  ISA16_RISCV64,
16846  "c.lui",
16847  (uint16_t)0x6001,
16848  (uint16_t) 0xe003,
16849  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16850  {
16851  etiss_uint64 rd = 0;
16852  static BitArrayRange R_rd_0 (11,7);
16853  etiss_uint64 rd_0 = R_rd_0.read(ba);
16854  rd += rd_0;
16855  etiss_uint64 imm = 0;
16856  static BitArrayRange R_imm_17 (12,12);
16857  etiss_uint64 imm_17 = R_imm_17.read(ba);
16858  imm += imm_17<<17;
16859  static BitArrayRange R_imm_12 (6,2);
16860  etiss_int64 imm_12 = R_imm_12.read(ba);
16861  imm += imm_12<<12;
16862  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16863  partInit.getAffectedRegisters().add(reg_name[rd],64);
16864  partInit.getAffectedRegisters().add("instructionPointer",64);
16865  partInit.code() = std::string("//c.lui\n")+
16866  "etiss_uint32 exception = 0;\n"
16867  "etiss_uint32 temp = 0;\n"
16868  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16869  #if RISCV64_Pipeline1
16870  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16871  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16872  "etiss_uint32 num_stages = 4;\n"
16873  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16874  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16875  #endif
16876  #if RISCV64_Pipeline2
16877  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16878  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16879  "etiss_uint32 num_stages = 4;\n"
16880  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16881  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16882  #endif
16883 
16884  "etiss_int64 imm_extended = 0;\n"
16885 
16886 "if((" + toString(imm) + " & 0x20000)>>17 == 0)\n"
16887 "{\n"
16888  "imm_extended = 0;\n"
16889  #if RISCV64_DEBUG_CALL
16890  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16891  #endif
16892 "}\n"
16893 
16894 "else\n"
16895 "{\n"
16896  "imm_extended = 4294967295;\n"
16897  #if RISCV64_DEBUG_CALL
16898  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16899  #endif
16900  "imm_extended = (imm_extended << 32);\n"
16901  #if RISCV64_DEBUG_CALL
16902  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16903  #endif
16904  "imm_extended = imm_extended + 4294705152;\n"
16905  #if RISCV64_DEBUG_CALL
16906  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16907  #endif
16908 "}\n"
16909 "imm_extended = imm_extended + " + toString(imm) + ";\n"
16910 #if RISCV64_DEBUG_CALL
16911 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16912 #endif
16913 "if(" + toString(rd) + " == 0)\n"
16914 "{\n"
16915  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
16916 "}\n"
16917 
16918 "if(imm_extended == 0)\n"
16919 "{\n"
16920  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
16921 "}\n"
16922 
16923 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = imm_extended;\n"
16924 #if RISCV64_DEBUG_CALL
16925 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
16926 #endif
16927 
16928  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16929 
16930  "return exception;\n"
16931 ;
16932 return true;
16933 },
16934 0,
16935 nullptr
16936 );
16937 //-------------------------------------------------------------------------------------------------------------------
16938 static InstructionDefinition c_addi16sp_imm(
16939  ISA16_RISCV64,
16940  "c.addi16sp",
16941  (uint16_t)0x6101,
16942  (uint16_t) 0xef83,
16943  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16944  {
16945  etiss_int64 imm = 0;
16946  static BitArrayRange R_imm_9 (12,12);
16947  etiss_int64 imm_9 = R_imm_9.read(ba);
16948  imm += imm_9<<9;
16949  static BitArrayRange R_imm_4 (6,6);
16950  etiss_int64 imm_4 = R_imm_4.read(ba);
16951  imm += imm_4<<4;
16952  static BitArrayRange R_imm_6 (5,5);
16953  etiss_int64 imm_6 = R_imm_6.read(ba);
16954  imm += imm_6<<6;
16955  static BitArrayRange R_imm_7 (4,3);
16956  etiss_int64 imm_7 = R_imm_7.read(ba);
16957  imm += imm_7<<7;
16958  static BitArrayRange R_imm_5 (2,2);
16959  etiss_int64 imm_5 = R_imm_5.read(ba);
16960  imm += imm_5<<5;
16961  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16962  partInit.getRegisterDependencies().add(reg_name[2],64);
16963  partInit.getAffectedRegisters().add(reg_name[2],64);
16964  partInit.getAffectedRegisters().add("instructionPointer",64);
16965  partInit.code() = std::string("//c.addi16sp\n")+
16966  "etiss_uint32 temp = 0;\n"
16967  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16968  #if RISCV64_Pipeline1
16969  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16970  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16971  "etiss_uint32 num_stages = 4;\n"
16972  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16973  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16974  #endif
16975  #if RISCV64_Pipeline2
16976  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16977  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16978  "etiss_uint32 num_stages = 4;\n"
16979  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16980  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16981  #endif
16982 
16983  "etiss_int64 imm_extended = 0;\n"
16984 
16985 "if((" + toString(imm) + " & 0x200)>>9 == 0)\n"
16986 "{\n"
16987  "imm_extended = 0;\n"
16988  #if RISCV64_DEBUG_CALL
16989  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16990  #endif
16991 "}\n"
16992 
16993 "else\n"
16994 "{\n"
16995  "imm_extended = 4294967295;\n"
16996  #if RISCV64_DEBUG_CALL
16997  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16998  #endif
16999  "imm_extended = (imm_extended << 32);\n"
17000  #if RISCV64_DEBUG_CALL
17001  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17002  #endif
17003  "imm_extended = imm_extended + 4294966272;\n"
17004  #if RISCV64_DEBUG_CALL
17005  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17006  #endif
17007 "}\n"
17008 "imm_extended = imm_extended + " + toString(imm) + ";\n"
17009 #if RISCV64_DEBUG_CALL
17010 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17011 #endif
17012 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[2]; \n"
17013 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17014 "{\n"
17015  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17016 "}\n"
17017 "*((RISCV64*)cpu)->X[2] = (etiss_int64)cast_0 + imm_extended;\n"
17018 #if RISCV64_DEBUG_CALL
17019 "printf(\"*((RISCV64*)cpu)->X[2] = %#lx\\n\",*((RISCV64*)cpu)->X[2]); \n"
17020 #endif
17021 
17022  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17023 
17024 ;
17025 return true;
17026 },
17027 0,
17028 nullptr
17029 );
17030 //-------------------------------------------------------------------------------------------------------------------
17031 static InstructionDefinition c_ld_8_rd_uimm_8_rs1_(
17032  ISA16_RISCV64,
17033  "c.ld",
17034  (uint16_t)0x6000,
17035  (uint16_t) 0xe003,
17036  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17037  {
17038  etiss_uint64 rs1 = 0;
17039  static BitArrayRange R_rs1_0 (9,7);
17040  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17041  rs1 += rs1_0;
17042  etiss_uint64 uimm = 0;
17043  static BitArrayRange R_uimm_3 (12,10);
17044  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
17045  uimm += uimm_3<<3;
17046  static BitArrayRange R_uimm_6 (6,5);
17047  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
17048  uimm += uimm_6<<6;
17049  etiss_uint64 rd = 0;
17050  static BitArrayRange R_rd_0 (4,2);
17051  etiss_uint64 rd_0 = R_rd_0.read(ba);
17052  rd += rd_0;
17053  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17054  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
17055  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17056  partInit.getAffectedRegisters().add("instructionPointer",64);
17057  partInit.code() = std::string("//c.ld\n")+
17058  "etiss_uint32 exception = 0;\n"
17059  "etiss_uint32 temp = 0;\n"
17060  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17061  #if RISCV64_Pipeline1
17062  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17063  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17064  "etiss_uint32 num_stages = 4;\n"
17065  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17066  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17067  #endif
17068  #if RISCV64_Pipeline2
17069  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17070  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17071  "etiss_uint32 num_stages = 4;\n"
17072  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17073  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17074  #endif
17075 
17076  "etiss_uint64 offs = 0;\n"
17077 
17078 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
17079 #if RISCV64_DEBUG_CALL
17080 "printf(\"offs = %#lx\\n\",offs); \n"
17081 #endif
17082  "etiss_uint64 MEM_offs;\n"
17083 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
17084 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
17085 "etiss_int64 cast_0 = MEM_offs; \n"
17086 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17087 "{\n"
17088  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17089 "}\n"
17090 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = (etiss_int64)cast_0;\n"
17091 #if RISCV64_DEBUG_CALL
17092 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
17093 #endif
17094 
17095  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17096 
17097  "return exception;\n"
17098 ;
17099 return true;
17100 },
17101 0,
17102 nullptr
17103 );
17104 //-------------------------------------------------------------------------------------------------------------------
17105 static InstructionDefinition c_ldsp_rd_uimm_sp_(
17106  ISA16_RISCV64,
17107  "c.ldsp",
17108  (uint16_t)0x6002,
17109  (uint16_t) 0xe003,
17110  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17111  {
17112  etiss_uint64 uimm = 0;
17113  static BitArrayRange R_uimm_5 (12,12);
17114  etiss_uint64 uimm_5 = R_uimm_5.read(ba);
17115  uimm += uimm_5<<5;
17116  static BitArrayRange R_uimm_3 (6,5);
17117  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
17118  uimm += uimm_3<<3;
17119  static BitArrayRange R_uimm_6 (4,2);
17120  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
17121  uimm += uimm_6<<6;
17122  etiss_uint64 rd = 0;
17123  static BitArrayRange R_rd_0 (11,7);
17124  etiss_uint64 rd_0 = R_rd_0.read(ba);
17125  rd += rd_0;
17126  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17127  partInit.getRegisterDependencies().add(reg_name[2],64);
17128  partInit.getAffectedRegisters().add(reg_name[rd],64);
17129  partInit.getAffectedRegisters().add("instructionPointer",64);
17130  partInit.code() = std::string("//c.ldsp\n")+
17131  "etiss_uint32 exception = 0;\n"
17132  "etiss_uint32 temp = 0;\n"
17133  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17134  #if RISCV64_Pipeline1
17135  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17136  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17137  "etiss_uint32 num_stages = 4;\n"
17138  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17139  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17140  #endif
17141  #if RISCV64_Pipeline2
17142  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17143  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17144  "etiss_uint32 num_stages = 4;\n"
17145  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17146  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17147  #endif
17148 
17149  "etiss_uint64 offs = 0;\n"
17150 
17151 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
17152 #if RISCV64_DEBUG_CALL
17153 "printf(\"offs = %#lx\\n\",offs); \n"
17154 #endif
17155 "if(" + toString(rd) + " != 0)\n"
17156 "{\n"
17157  "etiss_uint64 MEM_offs;\n"
17158  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
17159  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
17160  "etiss_int64 cast_0 = MEM_offs; \n"
17161  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17162  "{\n"
17163  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17164  "}\n"
17165  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
17166  #if RISCV64_DEBUG_CALL
17167  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
17168  #endif
17169 "}\n"
17170 
17171 
17172  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17173 
17174  "return exception;\n"
17175 ;
17176 return true;
17177 },
17178 0,
17179 nullptr
17180 );
17181 //-------------------------------------------------------------------------------------------------------------------
17182 static InstructionDefinition c_srli_8_rs1_shamt(
17183  ISA16_RISCV64,
17184  "c.srli",
17185  (uint16_t)0x8001,
17186  (uint16_t) 0xec03,
17187  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17188  {
17189  etiss_uint64 rs1 = 0;
17190  static BitArrayRange R_rs1_0 (9,7);
17191  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17192  rs1 += rs1_0;
17193  etiss_uint64 shamt = 0;
17194  static BitArrayRange R_shamt_5 (12,12);
17195  etiss_uint64 shamt_5 = R_shamt_5.read(ba);
17196  shamt += shamt_5<<5;
17197  static BitArrayRange R_shamt_0 (6,2);
17198  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
17199  shamt += shamt_0;
17200  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17201  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
17202  partInit.getAffectedRegisters().add(reg_name[rs1+8],64);
17203  partInit.getAffectedRegisters().add("instructionPointer",64);
17204  partInit.code() = std::string("//c.srli\n")+
17205  "etiss_uint32 temp = 0;\n"
17206  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17207  #if RISCV64_Pipeline1
17208  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17209  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17210  "etiss_uint32 num_stages = 4;\n"
17211  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17212  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17213  #endif
17214  #if RISCV64_Pipeline2
17215  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17216  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17217  "etiss_uint32 num_stages = 4;\n"
17218  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17219  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17220  #endif
17221 
17222  "etiss_int8 rs1_idx = 0;\n"
17223 
17224 "rs1_idx = " + toString(rs1) + " + 8;\n"
17225 #if RISCV64_DEBUG_CALL
17226 "printf(\"rs1_idx = %#x\\n\",rs1_idx); \n"
17227 #endif
17228 "*((RISCV64*)cpu)->X[rs1_idx] = (*((RISCV64*)cpu)->X[rs1_idx] >> " + toString(shamt) + ");\n"
17229 #if RISCV64_DEBUG_CALL
17230 "printf(\"*((RISCV64*)cpu)->X[rs1_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rs1_idx]); \n"
17231 #endif
17232 
17233  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17234 
17235 ;
17236 return true;
17237 },
17238 0,
17239 nullptr
17240 );
17241 //-------------------------------------------------------------------------------------------------------------------
17242 static InstructionDefinition c_srai_8_rs1_shamt(
17243  ISA16_RISCV64,
17244  "c.srai",
17245  (uint16_t)0x8401,
17246  (uint16_t) 0xec03,
17247  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17248  {
17249  etiss_uint64 rs1 = 0;
17250  static BitArrayRange R_rs1_0 (9,7);
17251  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17252  rs1 += rs1_0;
17253  etiss_uint64 shamt = 0;
17254  static BitArrayRange R_shamt_5 (12,12);
17255  etiss_uint64 shamt_5 = R_shamt_5.read(ba);
17256  shamt += shamt_5<<5;
17257  static BitArrayRange R_shamt_0 (6,2);
17258  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
17259  shamt += shamt_0;
17260  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17261  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
17262  partInit.getAffectedRegisters().add(reg_name[rs1+8],64);
17263  partInit.getAffectedRegisters().add("instructionPointer",64);
17264  partInit.code() = std::string("//c.srai\n")+
17265  "etiss_uint32 temp = 0;\n"
17266  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17267  #if RISCV64_Pipeline1
17268  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17269  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17270  "etiss_uint32 num_stages = 4;\n"
17271  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17272  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17273  #endif
17274  #if RISCV64_Pipeline2
17275  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17276  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17277  "etiss_uint32 num_stages = 4;\n"
17278  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17279  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17280  #endif
17281 
17282  "etiss_int8 rs1_idx = 0;\n"
17283 
17284 "rs1_idx = " + toString(rs1) + " + 8;\n"
17285 #if RISCV64_DEBUG_CALL
17286 "printf(\"rs1_idx = %#x\\n\",rs1_idx); \n"
17287 #endif
17288 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[rs1_idx]; \n"
17289 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17290 "{\n"
17291  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17292 "}\n"
17293 "*((RISCV64*)cpu)->X[rs1_idx] = ((etiss_int64)cast_0 >> " + toString(shamt) + ");\n"
17294 #if RISCV64_DEBUG_CALL
17295 "printf(\"*((RISCV64*)cpu)->X[rs1_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rs1_idx]); \n"
17296 #endif
17297 
17298  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17299 
17300 ;
17301 return true;
17302 },
17303 0,
17304 nullptr
17305 );
17306 //-------------------------------------------------------------------------------------------------------------------
17307 static InstructionDefinition c_andi_8_rs1_imm(
17308  ISA16_RISCV64,
17309  "c.andi",
17310  (uint16_t)0x8801,
17311  (uint16_t) 0xec03,
17312  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17313  {
17314  etiss_uint64 rs1 = 0;
17315  static BitArrayRange R_rs1_0 (9,7);
17316  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17317  rs1 += rs1_0;
17318  etiss_int64 imm = 0;
17319  static BitArrayRange R_imm_5 (12,12);
17320  etiss_int64 imm_5 = R_imm_5.read(ba);
17321  imm += imm_5<<5;
17322  static BitArrayRange R_imm_0 (6,2);
17323  etiss_int64 imm_0 = R_imm_0.read(ba);
17324  imm += imm_0;
17325  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17326  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
17327  partInit.getAffectedRegisters().add(reg_name[rs1+8],64);
17328  partInit.getAffectedRegisters().add("instructionPointer",64);
17329  partInit.code() = std::string("//c.andi\n")+
17330  "etiss_uint32 temp = 0;\n"
17331  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17332  #if RISCV64_Pipeline1
17333  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17334  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17335  "etiss_uint32 num_stages = 4;\n"
17336  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17337  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17338  #endif
17339  #if RISCV64_Pipeline2
17340  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17341  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17342  "etiss_uint32 num_stages = 4;\n"
17343  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17344  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17345  #endif
17346 
17347  "etiss_int64 imm_extended = 0;\n"
17348  "etiss_int8 rs1_idx = 0;\n"
17349 
17350 "if((" + toString(imm) + " & 0x20)>>5 == 0)\n"
17351 "{\n"
17352  "imm_extended = 0;\n"
17353  #if RISCV64_DEBUG_CALL
17354  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
17355  #endif
17356 "}\n"
17357 
17358 "else\n"
17359 "{\n"
17360  "imm_extended = 4294967295;\n"
17361  #if RISCV64_DEBUG_CALL
17362  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
17363  #endif
17364  "imm_extended = (imm_extended << 32);\n"
17365  #if RISCV64_DEBUG_CALL
17366  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17367  #endif
17368  "imm_extended = imm_extended + 4294967232;\n"
17369  #if RISCV64_DEBUG_CALL
17370  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17371  #endif
17372 "}\n"
17373 "imm_extended = imm_extended + " + toString(imm) + ";\n"
17374 #if RISCV64_DEBUG_CALL
17375 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17376 #endif
17377 "rs1_idx = " + toString(rs1) + " + 8;\n"
17378 #if RISCV64_DEBUG_CALL
17379 "printf(\"rs1_idx = %#x\\n\",rs1_idx); \n"
17380 #endif
17381 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[rs1_idx]; \n"
17382 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17383 "{\n"
17384  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17385 "}\n"
17386 "*((RISCV64*)cpu)->X[rs1_idx] = ((etiss_int64)cast_0 & imm_extended);\n"
17387 #if RISCV64_DEBUG_CALL
17388 "printf(\"*((RISCV64*)cpu)->X[rs1_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rs1_idx]); \n"
17389 #endif
17390 
17391  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17392 
17393 ;
17394 return true;
17395 },
17396 0,
17397 nullptr
17398 );
17399 //-------------------------------------------------------------------------------------------------------------------
17400 static InstructionDefinition c_sub_8_rd_8_rs2(
17401  ISA16_RISCV64,
17402  "c.sub",
17403  (uint16_t)0x8c01,
17404  (uint16_t) 0xfc63,
17405  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17406  {
17407  etiss_uint64 rs2 = 0;
17408  static BitArrayRange R_rs2_0 (4,2);
17409  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17410  rs2 += rs2_0;
17411  etiss_uint64 rd = 0;
17412  static BitArrayRange R_rd_0 (9,7);
17413  etiss_uint64 rd_0 = R_rd_0.read(ba);
17414  rd += rd_0;
17415  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17416  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17417  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17418  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17419  partInit.getAffectedRegisters().add("instructionPointer",64);
17420  partInit.code() = std::string("//c.sub\n")+
17421  "etiss_uint32 temp = 0;\n"
17422  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17423  #if RISCV64_Pipeline1
17424  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17425  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17426  "etiss_uint32 num_stages = 4;\n"
17427  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17428  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17429  #endif
17430  #if RISCV64_Pipeline2
17431  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17432  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17433  "etiss_uint32 num_stages = 4;\n"
17434  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17435  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17436  #endif
17437 
17438  "etiss_int8 rd_idx = 0;\n"
17439 
17440 "rd_idx = " + toString(rd) + " + 8;\n"
17441 #if RISCV64_DEBUG_CALL
17442 "printf(\"rd_idx = %#x\\n\",rd_idx); \n"
17443 #endif
17444 "*((RISCV64*)cpu)->X[rd_idx] = *((RISCV64*)cpu)->X[rd_idx] - *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8];\n"
17445 #if RISCV64_DEBUG_CALL
17446 "printf(\"*((RISCV64*)cpu)->X[rd_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rd_idx]); \n"
17447 #endif
17448 
17449  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17450 
17451 ;
17452 return true;
17453 },
17454 0,
17455 nullptr
17456 );
17457 //-------------------------------------------------------------------------------------------------------------------
17458 static InstructionDefinition c_xor_8_rd_8_rs2(
17459  ISA16_RISCV64,
17460  "c.xor",
17461  (uint16_t)0x8c21,
17462  (uint16_t) 0xfc63,
17463  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17464  {
17465  etiss_uint64 rs2 = 0;
17466  static BitArrayRange R_rs2_0 (4,2);
17467  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17468  rs2 += rs2_0;
17469  etiss_uint64 rd = 0;
17470  static BitArrayRange R_rd_0 (9,7);
17471  etiss_uint64 rd_0 = R_rd_0.read(ba);
17472  rd += rd_0;
17473  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17474  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17475  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17476  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17477  partInit.getAffectedRegisters().add("instructionPointer",64);
17478  partInit.code() = std::string("//c.xor\n")+
17479  "etiss_uint32 temp = 0;\n"
17480  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17481  #if RISCV64_Pipeline1
17482  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17483  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17484  "etiss_uint32 num_stages = 4;\n"
17485  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17486  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17487  #endif
17488  #if RISCV64_Pipeline2
17489  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17490  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17491  "etiss_uint32 num_stages = 4;\n"
17492  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17493  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17494  #endif
17495 
17496  "etiss_int8 rd_idx = 0;\n"
17497 
17498 "rd_idx = " + toString(rd) + " + 8;\n"
17499 #if RISCV64_DEBUG_CALL
17500 "printf(\"rd_idx = %#x\\n\",rd_idx); \n"
17501 #endif
17502 "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] ^ *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8]);\n"
17503 #if RISCV64_DEBUG_CALL
17504 "printf(\"*((RISCV64*)cpu)->X[rd_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rd_idx]); \n"
17505 #endif
17506 
17507  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17508 
17509 ;
17510 return true;
17511 },
17512 0,
17513 nullptr
17514 );
17515 //-------------------------------------------------------------------------------------------------------------------
17516 static InstructionDefinition c_or_8_rd_8_rs2(
17517  ISA16_RISCV64,
17518  "c.or",
17519  (uint16_t)0x8c41,
17520  (uint16_t) 0xfc63,
17521  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17522  {
17523  etiss_uint64 rs2 = 0;
17524  static BitArrayRange R_rs2_0 (4,2);
17525  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17526  rs2 += rs2_0;
17527  etiss_uint64 rd = 0;
17528  static BitArrayRange R_rd_0 (9,7);
17529  etiss_uint64 rd_0 = R_rd_0.read(ba);
17530  rd += rd_0;
17531  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17532  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17533  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17534  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17535  partInit.getAffectedRegisters().add("instructionPointer",64);
17536  partInit.code() = std::string("//c.or\n")+
17537  "etiss_uint32 temp = 0;\n"
17538  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17539  #if RISCV64_Pipeline1
17540  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17541  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17542  "etiss_uint32 num_stages = 4;\n"
17543  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17544  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17545  #endif
17546  #if RISCV64_Pipeline2
17547  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17548  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17549  "etiss_uint32 num_stages = 4;\n"
17550  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17551  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17552  #endif
17553 
17554  "etiss_int8 rd_idx = 0;\n"
17555 
17556 "rd_idx = " + toString(rd) + " + 8;\n"
17557 #if RISCV64_DEBUG_CALL
17558 "printf(\"rd_idx = %#x\\n\",rd_idx); \n"
17559 #endif
17560 "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] | *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8]);\n"
17561 #if RISCV64_DEBUG_CALL
17562 "printf(\"*((RISCV64*)cpu)->X[rd_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rd_idx]); \n"
17563 #endif
17564 
17565  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17566 
17567 ;
17568 return true;
17569 },
17570 0,
17571 nullptr
17572 );
17573 //-------------------------------------------------------------------------------------------------------------------
17574 static InstructionDefinition c_and_8_rd_8_rs2(
17575  ISA16_RISCV64,
17576  "c.and",
17577  (uint16_t)0x8c61,
17578  (uint16_t) 0xfc63,
17579  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17580  {
17581  etiss_uint64 rs2 = 0;
17582  static BitArrayRange R_rs2_0 (4,2);
17583  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17584  rs2 += rs2_0;
17585  etiss_uint64 rd = 0;
17586  static BitArrayRange R_rd_0 (9,7);
17587  etiss_uint64 rd_0 = R_rd_0.read(ba);
17588  rd += rd_0;
17589  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17590  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17591  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17592  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17593  partInit.getAffectedRegisters().add("instructionPointer",64);
17594  partInit.code() = std::string("//c.and\n")+
17595  "etiss_uint32 temp = 0;\n"
17596  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17597  #if RISCV64_Pipeline1
17598  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17599  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17600  "etiss_uint32 num_stages = 4;\n"
17601  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17602  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17603  #endif
17604  #if RISCV64_Pipeline2
17605  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17606  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17607  "etiss_uint32 num_stages = 4;\n"
17608  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17609  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17610  #endif
17611 
17612  "etiss_int8 rd_idx = 0;\n"
17613 
17614 "rd_idx = " + toString(rd) + " + 8;\n"
17615 #if RISCV64_DEBUG_CALL
17616 "printf(\"rd_idx = %#x\\n\",rd_idx); \n"
17617 #endif
17618 "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] & *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8]);\n"
17619 #if RISCV64_DEBUG_CALL
17620 "printf(\"*((RISCV64*)cpu)->X[rd_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rd_idx]); \n"
17621 #endif
17622 
17623  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17624 
17625 ;
17626 return true;
17627 },
17628 0,
17629 nullptr
17630 );
17631 //-------------------------------------------------------------------------------------------------------------------
17632 static InstructionDefinition c_mv_rd_rs2(
17633  ISA16_RISCV64,
17634  "c.mv",
17635  (uint16_t)0x8002,
17636  (uint16_t) 0xf003,
17637  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17638  {
17639  etiss_uint64 rs2 = 0;
17640  static BitArrayRange R_rs2_0 (6,2);
17641  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17642  rs2 += rs2_0;
17643  etiss_uint64 rd = 0;
17644  static BitArrayRange R_rd_0 (11,7);
17645  etiss_uint64 rd_0 = R_rd_0.read(ba);
17646  rd += rd_0;
17647  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17648  partInit.getRegisterDependencies().add(reg_name[rs2],64);
17649  partInit.getAffectedRegisters().add(reg_name[rd],64);
17650  partInit.getAffectedRegisters().add("instructionPointer",64);
17651  partInit.code() = std::string("//c.mv\n")+
17652  "etiss_uint32 temp = 0;\n"
17653  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17654  #if RISCV64_Pipeline1
17655  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17656  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17657  "etiss_uint32 num_stages = 4;\n"
17658  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17659  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17660  #endif
17661  #if RISCV64_Pipeline2
17662  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17663  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17664  "etiss_uint32 num_stages = 4;\n"
17665  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17666  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17667  #endif
17668 
17669 
17670 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
17671 #if RISCV64_DEBUG_CALL
17672 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
17673 #endif
17674 
17675  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17676 
17677 ;
17678 return true;
17679 },
17680 0,
17681 nullptr
17682 );
17683 //-------------------------------------------------------------------------------------------------------------------
17684 static InstructionDefinition c_jr_rs1(
17685  ISA16_RISCV64,
17686  "c.jr",
17687  (uint16_t)0x8002,
17688  (uint16_t) 0xf07f,
17689  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17690  {
17691  etiss_uint64 rs1 = 0;
17692  static BitArrayRange R_rs1_0 (11,7);
17693  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17694  rs1 += rs1_0;
17695  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17696  partInit.getRegisterDependencies().add(reg_name[rs1],64);
17697  partInit.getAffectedRegisters().add("instructionPointer",64);
17698  partInit.code() = std::string("//c.jr\n")+
17699  "etiss_uint32 temp = 0;\n"
17700  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17701  #if RISCV64_Pipeline1
17702  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17703  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17704  "etiss_uint32 num_stages = 4;\n"
17705  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17706  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17707  #endif
17708  #if RISCV64_Pipeline2
17709  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17710  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17711  "etiss_uint32 num_stages = 4;\n"
17712  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17713  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17714  #endif
17715 
17716 
17717 "cpu->instructionPointer = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
17718 #if RISCV64_DEBUG_CALL
17719 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
17720 #endif
17721 
17722  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
17723 
17724  "return 0;\n"
17725 ;
17726 return true;
17727 },
17728 0,
17729 nullptr
17730 );
17731 //-------------------------------------------------------------------------------------------------------------------
17732 static InstructionDefinition c_add_rd_rs2(
17733  ISA16_RISCV64,
17734  "c.add",
17735  (uint16_t)0x9002,
17736  (uint16_t) 0xf003,
17737  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17738  {
17739  etiss_uint64 rs2 = 0;
17740  static BitArrayRange R_rs2_0 (6,2);
17741  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17742  rs2 += rs2_0;
17743  etiss_uint64 rd = 0;
17744  static BitArrayRange R_rd_0 (11,7);
17745  etiss_uint64 rd_0 = R_rd_0.read(ba);
17746  rd += rd_0;
17747  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17748  partInit.getRegisterDependencies().add(reg_name[rs2],64);
17749  partInit.getRegisterDependencies().add(reg_name[rd],64);
17750  partInit.getAffectedRegisters().add(reg_name[rd],64);
17751  partInit.getAffectedRegisters().add("instructionPointer",64);
17752  partInit.code() = std::string("//c.add\n")+
17753  "etiss_uint32 temp = 0;\n"
17754  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17755  #if RISCV64_Pipeline1
17756  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17757  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17758  "etiss_uint32 num_stages = 4;\n"
17759  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17760  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17761  #endif
17762  #if RISCV64_Pipeline2
17763  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17764  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17765  "etiss_uint32 num_stages = 4;\n"
17766  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17767  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17768  #endif
17769 
17770 
17771 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rd) + "] + *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
17772 #if RISCV64_DEBUG_CALL
17773 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
17774 #endif
17775 
17776  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17777 
17778 ;
17779 return true;
17780 },
17781 0,
17782 nullptr
17783 );
17784 //-------------------------------------------------------------------------------------------------------------------
17785 static InstructionDefinition c_jalr_rs1(
17786  ISA16_RISCV64,
17787  "c.jalr",
17788  (uint16_t)0x9002,
17789  (uint16_t) 0xf07f,
17790  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17791  {
17792  etiss_uint64 rs1 = 0;
17793  static BitArrayRange R_rs1_0 (11,7);
17794  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17795  rs1 += rs1_0;
17796  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17797  partInit.getRegisterDependencies().add(reg_name[rs1],64);
17798  partInit.getAffectedRegisters().add(reg_name[1],64);
17799  partInit.getAffectedRegisters().add("instructionPointer",64);
17800  partInit.code() = std::string("//c.jalr\n")+
17801  "etiss_uint32 temp = 0;\n"
17802  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17803  #if RISCV64_Pipeline1
17804  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17805  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17806  "etiss_uint32 num_stages = 4;\n"
17807  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17808  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17809  #endif
17810  #if RISCV64_Pipeline2
17811  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17812  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17813  "etiss_uint32 num_stages = 4;\n"
17814  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17815  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17816  #endif
17817 
17818 
17819 "*((RISCV64*)cpu)->X[1] = " +toString((uint64_t)ic.current_address_)+"ULL + 2;\n"
17820 #if RISCV64_DEBUG_CALL
17821 "printf(\"*((RISCV64*)cpu)->X[1] = %#lx\\n\",*((RISCV64*)cpu)->X[1]); \n"
17822 #endif
17823 "cpu->instructionPointer = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
17824 #if RISCV64_DEBUG_CALL
17825 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
17826 #endif
17827 
17828  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
17829 
17830  "return 0;\n"
17831 ;
17832 return true;
17833 },
17834 0,
17835 nullptr
17836 );
17837 //-------------------------------------------------------------------------------------------------------------------
17838 static InstructionDefinition c_ebreak_(
17839  ISA16_RISCV64,
17840  "c.ebreak",
17841  (uint16_t)0x9002,
17842  (uint16_t) 0xffff,
17843  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17844  {
17845  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17846  partInit.getAffectedRegisters().add("instructionPointer",64);
17847  partInit.code() = std::string("//c.ebreak\n")+
17848  "etiss_uint32 exception = 0;\n"
17849  "etiss_uint32 temp = 0;\n"
17850  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17851  #if RISCV64_Pipeline1
17852  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17853  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17854  "etiss_uint32 num_stages = 4;\n"
17855  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17856  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17857  #endif
17858  #if RISCV64_Pipeline2
17859  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17860  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17861  "etiss_uint32 num_stages = 4;\n"
17862  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17863  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17864  #endif
17865 
17866 
17867 "return ETISS_RETURNCODE_CPUFINISHED; \n"
17868 
17869  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17870 
17871  "return exception;\n"
17872 ;
17873 return true;
17874 },
17875 0,
17876 nullptr
17877 );
17878 //-------------------------------------------------------------------------------------------------------------------
17879 static InstructionDefinition c_subw_8_rd_8_rd_8_rs2(
17880  ISA16_RISCV64,
17881  "c.subw",
17882  (uint16_t)0x9c01,
17883  (uint16_t) 0xfc63,
17884  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17885  {
17886  etiss_uint64 rs2 = 0;
17887  static BitArrayRange R_rs2_0 (4,2);
17888  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17889  rs2 += rs2_0;
17890  etiss_uint64 rd = 0;
17891  static BitArrayRange R_rd_0 (9,7);
17892  etiss_uint64 rd_0 = R_rd_0.read(ba);
17893  rd += rd_0;
17894  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17895  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17896  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17897  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17898  partInit.getAffectedRegisters().add("instructionPointer",64);
17899  partInit.code() = std::string("//c.subw\n")+
17900  "etiss_uint32 temp = 0;\n"
17901  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17902  #if RISCV64_Pipeline1
17903  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17904  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17905  "etiss_uint32 num_stages = 4;\n"
17906  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17907  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17908  #endif
17909  #if RISCV64_Pipeline2
17910  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17911  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17912  "etiss_uint32 num_stages = 4;\n"
17913  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17914  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17915  #endif
17916 
17917  "etiss_uint32 res = 0;\n"
17918 
17919 "res = (*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] & 0xffffffff) - (*((RISCV64*)cpu)->X[" + toString(rs2) + " + 8] & 0xffffffff);\n"
17920 #if RISCV64_DEBUG_CALL
17921 "printf(\"res = %#x\\n\",res); \n"
17922 #endif
17923 "etiss_int32 cast_0 = res; \n"
17924 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
17925 "{\n"
17926  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
17927 "}\n"
17928 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = (etiss_int64)cast_0;\n"
17929 #if RISCV64_DEBUG_CALL
17930 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
17931 #endif
17932 
17933  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17934 
17935 ;
17936 return true;
17937 },
17938 0,
17939 nullptr
17940 );
17941 //-------------------------------------------------------------------------------------------------------------------
17942 static InstructionDefinition c_addw_8_rd_8_rd_8_rs2(
17943  ISA16_RISCV64,
17944  "c.addw",
17945  (uint16_t)0x9c21,
17946  (uint16_t) 0xfc63,
17947  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17948  {
17949  etiss_uint64 rs2 = 0;
17950  static BitArrayRange R_rs2_0 (4,2);
17951  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17952  rs2 += rs2_0;
17953  etiss_uint64 rd = 0;
17954  static BitArrayRange R_rd_0 (9,7);
17955  etiss_uint64 rd_0 = R_rd_0.read(ba);
17956  rd += rd_0;
17957  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17958  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17959  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17960  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17961  partInit.getAffectedRegisters().add("instructionPointer",64);
17962  partInit.code() = std::string("//c.addw\n")+
17963  "etiss_uint32 temp = 0;\n"
17964  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17965  #if RISCV64_Pipeline1
17966  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17967  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17968  "etiss_uint32 num_stages = 4;\n"
17969  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17970  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17971  #endif
17972  #if RISCV64_Pipeline2
17973  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17974  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17975  "etiss_uint32 num_stages = 4;\n"
17976  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17977  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17978  #endif
17979 
17980  "etiss_uint32 res = 0;\n"
17981 
17982 "res = (*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] & 0xffffffff) + (*((RISCV64*)cpu)->X[" + toString(rs2) + " + 8] & 0xffffffff);\n"
17983 #if RISCV64_DEBUG_CALL
17984 "printf(\"res = %#x\\n\",res); \n"
17985 #endif
17986 "etiss_int32 cast_0 = res; \n"
17987 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
17988 "{\n"
17989  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
17990 "}\n"
17991 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = (etiss_int64)cast_0;\n"
17992 #if RISCV64_DEBUG_CALL
17993 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
17994 #endif
17995 
17996  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17997 
17998 ;
17999 return true;
18000 },
18001 0,
18002 nullptr
18003 );
18004 //-------------------------------------------------------------------------------------------------------------------
18005 static InstructionDefinition c_j_imm(
18006  ISA16_RISCV64,
18007  "c.j",
18008  (uint16_t)0xa001,
18009  (uint16_t) 0xe003,
18010  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18011  {
18012  etiss_int64 imm = 0;
18013  static BitArrayRange R_imm_11 (12,12);
18014  etiss_int64 imm_11 = R_imm_11.read(ba);
18015  imm += imm_11<<11;
18016  static BitArrayRange R_imm_4 (11,11);
18017  etiss_int64 imm_4 = R_imm_4.read(ba);
18018  imm += imm_4<<4;
18019  static BitArrayRange R_imm_8 (10,9);
18020  etiss_int64 imm_8 = R_imm_8.read(ba);
18021  imm += imm_8<<8;
18022  static BitArrayRange R_imm_10 (8,8);
18023  etiss_int64 imm_10 = R_imm_10.read(ba);
18024  imm += imm_10<<10;
18025  static BitArrayRange R_imm_6 (7,7);
18026  etiss_int64 imm_6 = R_imm_6.read(ba);
18027  imm += imm_6<<6;
18028  static BitArrayRange R_imm_7 (6,6);
18029  etiss_int64 imm_7 = R_imm_7.read(ba);
18030  imm += imm_7<<7;
18031  static BitArrayRange R_imm_1 (5,3);
18032  etiss_int64 imm_1 = R_imm_1.read(ba);
18033  imm += imm_1<<1;
18034  static BitArrayRange R_imm_5 (2,2);
18035  etiss_int64 imm_5 = R_imm_5.read(ba);
18036  imm += imm_5<<5;
18037  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18038  partInit.getAffectedRegisters().add("instructionPointer",64);
18039  partInit.code() = std::string("//c.j\n")+
18040  "etiss_uint32 temp = 0;\n"
18041  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18042  #if RISCV64_Pipeline1
18043  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18044  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18045  "etiss_uint32 num_stages = 4;\n"
18046  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18047  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18048  #endif
18049  #if RISCV64_Pipeline2
18050  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18051  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18052  "etiss_uint32 num_stages = 4;\n"
18053  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18054  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18055  #endif
18056 
18057  "etiss_int64 imm_extended = 0;\n"
18058 
18059 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
18060 "{\n"
18061  "imm_extended = 0;\n"
18062  #if RISCV64_DEBUG_CALL
18063  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
18064  #endif
18065 "}\n"
18066 
18067 "else\n"
18068 "{\n"
18069  "imm_extended = 4294967295;\n"
18070  #if RISCV64_DEBUG_CALL
18071  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
18072  #endif
18073  "imm_extended = (imm_extended << 32);\n"
18074  #if RISCV64_DEBUG_CALL
18075  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18076  #endif
18077  "imm_extended = imm_extended + 4294963200;\n"
18078  #if RISCV64_DEBUG_CALL
18079  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18080  #endif
18081 "}\n"
18082 "imm_extended = imm_extended + " + toString(imm) + ";\n"
18083 #if RISCV64_DEBUG_CALL
18084 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18085 #endif
18086 "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
18087 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
18088 "{\n"
18089  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
18090 "}\n"
18091 "cpu->instructionPointer = (etiss_int64)cast_0 + imm_extended;\n"
18092 #if RISCV64_DEBUG_CALL
18093 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
18094 #endif
18095 
18096  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
18097 
18098  "return 0;\n"
18099 ;
18100 return true;
18101 },
18102 0,
18103 nullptr
18104 );
18105 //-------------------------------------------------------------------------------------------------------------------
18106 static InstructionDefinition c_fsd_rs2_uimm_8_rs1_(
18107  ISA16_RISCV64,
18108  "c.fsd",
18109  (uint16_t)0xa000,
18110  (uint16_t) 0xe003,
18111  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18112  {
18113  etiss_uint64 rs2 = 0;
18114  static BitArrayRange R_rs2_0 (4,2);
18115  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
18116  rs2 += rs2_0;
18117  etiss_uint64 rs1 = 0;
18118  static BitArrayRange R_rs1_0 (9,7);
18119  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
18120  rs1 += rs1_0;
18121  etiss_uint64 uimm = 0;
18122  static BitArrayRange R_uimm_3 (12,10);
18123  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
18124  uimm += uimm_3<<3;
18125  static BitArrayRange R_uimm_6 (6,5);
18126  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
18127  uimm += uimm_6<<6;
18128  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18129  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
18130  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
18131  partInit.getAffectedRegisters().add("instructionPointer",64);
18132  partInit.code() = std::string("//c.fsd\n")+
18133  "etiss_uint32 exception = 0;\n"
18134  "etiss_uint32 temp = 0;\n"
18135  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18136  #if RISCV64_Pipeline1
18137  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18138  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18139  "etiss_uint32 num_stages = 4;\n"
18140  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18141  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18142  #endif
18143  #if RISCV64_Pipeline2
18144  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18145  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18146  "etiss_uint32 num_stages = 4;\n"
18147  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18148  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18149  #endif
18150 
18151  "etiss_uint64 offs = 0;\n"
18152 
18153 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
18154 #if RISCV64_DEBUG_CALL
18155 "printf(\"offs = %#lx\\n\",offs); \n"
18156 #endif
18157  "etiss_uint64 MEM_offs;\n"
18158 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
18159 "MEM_offs = (((RISCV64*)cpu)->F[" + toString(rs2) + " + 8] & 0xffffffffffffffff);\n"
18160 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
18161 #if RISCV64_DEBUG_CALL
18162 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
18163 #endif
18164 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
18165 "{\n"
18166  "((RISCV64*)cpu)->RES = 0;\n"
18167  #if RISCV64_DEBUG_CALL
18168  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
18169  #endif
18170 "}\n"
18171 
18172 
18173  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18174 
18175  "return exception;\n"
18176 ;
18177 return true;
18178 },
18179 0,
18180 nullptr
18181 );
18182 //-------------------------------------------------------------------------------------------------------------------
18183 static InstructionDefinition c_fsdsp_rs2_uimm_x2_(
18184  ISA16_RISCV64,
18185  "c.fsdsp",
18186  (uint16_t)0xa002,
18187  (uint16_t) 0xe003,
18188  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18189  {
18190  etiss_uint64 rs2 = 0;
18191  static BitArrayRange R_rs2_0 (6,2);
18192  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
18193  rs2 += rs2_0;
18194  etiss_uint64 uimm = 0;
18195  static BitArrayRange R_uimm_3 (12,10);
18196  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
18197  uimm += uimm_3<<3;
18198  static BitArrayRange R_uimm_6 (9,7);
18199  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
18200  uimm += uimm_6<<6;
18201  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18202  partInit.getRegisterDependencies().add(reg_name[2],64);
18203  partInit.getRegisterDependencies().add(reg_name[rs2],64);
18204  partInit.getAffectedRegisters().add("instructionPointer",64);
18205  partInit.code() = std::string("//c.fsdsp\n")+
18206  "etiss_uint32 exception = 0;\n"
18207  "etiss_uint32 temp = 0;\n"
18208  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18209  #if RISCV64_Pipeline1
18210  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18211  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18212  "etiss_uint32 num_stages = 4;\n"
18213  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18214  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18215  #endif
18216  #if RISCV64_Pipeline2
18217  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18218  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18219  "etiss_uint32 num_stages = 4;\n"
18220  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18221  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18222  #endif
18223 
18224  "etiss_uint64 offs = 0;\n"
18225 
18226 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
18227 #if RISCV64_DEBUG_CALL
18228 "printf(\"offs = %#lx\\n\",offs); \n"
18229 #endif
18230  "etiss_uint64 MEM_offs;\n"
18231 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
18232 "MEM_offs = (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff);\n"
18233 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
18234 #if RISCV64_DEBUG_CALL
18235 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
18236 #endif
18237 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
18238 "{\n"
18239  "((RISCV64*)cpu)->RES = 0;\n"
18240  #if RISCV64_DEBUG_CALL
18241  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
18242  #endif
18243 "}\n"
18244 
18245 
18246  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18247 
18248  "return exception;\n"
18249 ;
18250 return true;
18251 },
18252 0,
18253 nullptr
18254 );
18255 //-------------------------------------------------------------------------------------------------------------------
18256 static InstructionDefinition c_bnez_8_rs1_imm(
18257  ISA16_RISCV64,
18258  "c.bnez",
18259  (uint16_t)0xe001,
18260  (uint16_t) 0xe003,
18261  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18262  {
18263  etiss_uint64 rs1 = 0;
18264  static BitArrayRange R_rs1_0 (9,7);
18265  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
18266  rs1 += rs1_0;
18267  etiss_int64 imm = 0;
18268  static BitArrayRange R_imm_8 (12,12);
18269  etiss_int64 imm_8 = R_imm_8.read(ba);
18270  imm += imm_8<<8;
18271  static BitArrayRange R_imm_3 (11,10);
18272  etiss_int64 imm_3 = R_imm_3.read(ba);
18273  imm += imm_3<<3;
18274  static BitArrayRange R_imm_6 (6,5);
18275  etiss_int64 imm_6 = R_imm_6.read(ba);
18276  imm += imm_6<<6;
18277  static BitArrayRange R_imm_1 (4,3);
18278  etiss_int64 imm_1 = R_imm_1.read(ba);
18279  imm += imm_1<<1;
18280  static BitArrayRange R_imm_5 (2,2);
18281  etiss_int64 imm_5 = R_imm_5.read(ba);
18282  imm += imm_5<<5;
18283  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18284  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
18285  partInit.getAffectedRegisters().add("instructionPointer",64);
18286  partInit.code() = std::string("//c.bnez\n")+
18287  "etiss_uint32 temp = 0;\n"
18288  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18289  #if RISCV64_Pipeline1
18290  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18291  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18292  "etiss_uint32 num_stages = 4;\n"
18293  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18294  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18295  #endif
18296  #if RISCV64_Pipeline2
18297  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18298  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18299  "etiss_uint32 num_stages = 4;\n"
18300  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18301  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18302  #endif
18303 
18304  "etiss_int64 imm_extended = 0;\n"
18305  "etiss_int64 choose1 = 0;\n"
18306 
18307 "if((" + toString(imm) + " & 0x100)>>8 == 0)\n"
18308 "{\n"
18309  "imm_extended = 0;\n"
18310  #if RISCV64_DEBUG_CALL
18311  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
18312  #endif
18313 "}\n"
18314 
18315 "else\n"
18316 "{\n"
18317  "imm_extended = 4294967295;\n"
18318  #if RISCV64_DEBUG_CALL
18319  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
18320  #endif
18321  "imm_extended = (imm_extended << 32);\n"
18322  #if RISCV64_DEBUG_CALL
18323  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18324  #endif
18325  "imm_extended = imm_extended + 4294966784;\n"
18326  #if RISCV64_DEBUG_CALL
18327  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18328  #endif
18329 "}\n"
18330 "imm_extended = imm_extended + " + toString(imm) + ";\n"
18331 #if RISCV64_DEBUG_CALL
18332 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18333 #endif
18334 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] != 0)\n"
18335 "{\n"
18336  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
18337  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
18338  "{\n"
18339  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
18340  "}\n"
18341  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
18342  #if RISCV64_DEBUG_CALL
18343  "printf(\"choose1 = %#lx\\n\",choose1); \n"
18344  #endif
18345 // Explicit assignment to PC
18346 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18347 "}\n"
18348 
18349 "else\n"
18350 "{\n"
18351  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 2;\n"
18352  #if RISCV64_DEBUG_CALL
18353  "printf(\"choose1 = %#lx\\n\",choose1); \n"
18354  #endif
18355 "}\n"
18356 "cpu->instructionPointer = choose1;\n"
18357 #if RISCV64_DEBUG_CALL
18358 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
18359 #endif
18360 
18361  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
18362 
18363  "return 0;\n"
18364 ;
18365 return true;
18366 },
18367 0,
18368 nullptr
18369 );
18370 //-------------------------------------------------------------------------------------------------------------------
18371 static InstructionDefinition c_sd_8_rs2_uimm_8_rs1_(
18372  ISA16_RISCV64,
18373  "c.sd",
18374  (uint16_t)0xe000,
18375  (uint16_t) 0xe003,
18376  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18377  {
18378  etiss_uint64 rs2 = 0;
18379  static BitArrayRange R_rs2_0 (4,2);
18380  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
18381  rs2 += rs2_0;
18382  etiss_uint64 rs1 = 0;
18383  static BitArrayRange R_rs1_0 (9,7);
18384  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
18385  rs1 += rs1_0;
18386  etiss_uint64 uimm = 0;
18387  static BitArrayRange R_uimm_3 (12,10);
18388  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
18389  uimm += uimm_3<<3;
18390  static BitArrayRange R_uimm_6 (6,5);
18391  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
18392  uimm += uimm_6<<6;
18393  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18394  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
18395  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
18396  partInit.getAffectedRegisters().add("instructionPointer",64);
18397  partInit.code() = std::string("//c.sd\n")+
18398  "etiss_uint32 exception = 0;\n"
18399  "etiss_uint32 temp = 0;\n"
18400  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18401  #if RISCV64_Pipeline1
18402  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18403  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18404  "etiss_uint32 num_stages = 4;\n"
18405  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18406  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18407  #endif
18408  #if RISCV64_Pipeline2
18409  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18410  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18411  "etiss_uint32 num_stages = 4;\n"
18412  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18413  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18414  #endif
18415 
18416  "etiss_uint64 offs = 0;\n"
18417 
18418 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
18419 #if RISCV64_DEBUG_CALL
18420 "printf(\"offs = %#lx\\n\",offs); \n"
18421 #endif
18422  "etiss_uint64 MEM_offs;\n"
18423 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
18424 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8];\n"
18425 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
18426 #if RISCV64_DEBUG_CALL
18427 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
18428 #endif
18429 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
18430 "{\n"
18431  "((RISCV64*)cpu)->RES = 0;\n"
18432  #if RISCV64_DEBUG_CALL
18433  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
18434  #endif
18435 "}\n"
18436 
18437 
18438  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18439 
18440  "return exception;\n"
18441 ;
18442 return true;
18443 },
18444 0,
18445 nullptr
18446 );
18447 //-------------------------------------------------------------------------------------------------------------------
18448 static InstructionDefinition c_sdsp_rs2_uimm_sp_(
18449  ISA16_RISCV64,
18450  "c.sdsp",
18451  (uint16_t)0xe002,
18452  (uint16_t) 0xe003,
18453  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18454  {
18455  etiss_uint64 rs2 = 0;
18456  static BitArrayRange R_rs2_0 (6,2);
18457  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
18458  rs2 += rs2_0;
18459  etiss_uint64 uimm = 0;
18460  static BitArrayRange R_uimm_3 (12,10);
18461  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
18462  uimm += uimm_3<<3;
18463  static BitArrayRange R_uimm_6 (9,7);
18464  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
18465  uimm += uimm_6<<6;
18466  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18467  partInit.getRegisterDependencies().add(reg_name[rs2],64);
18468  partInit.getRegisterDependencies().add(reg_name[2],64);
18469  partInit.getAffectedRegisters().add("instructionPointer",64);
18470  partInit.code() = std::string("//c.sdsp\n")+
18471  "etiss_uint32 exception = 0;\n"
18472  "etiss_uint32 temp = 0;\n"
18473  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18474  #if RISCV64_Pipeline1
18475  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18476  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18477  "etiss_uint32 num_stages = 4;\n"
18478  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18479  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18480  #endif
18481  #if RISCV64_Pipeline2
18482  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18483  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18484  "etiss_uint32 num_stages = 4;\n"
18485  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18486  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18487  #endif
18488 
18489  "etiss_uint64 offs = 0;\n"
18490 
18491 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
18492 #if RISCV64_DEBUG_CALL
18493 "printf(\"offs = %#lx\\n\",offs); \n"
18494 #endif
18495  "etiss_uint64 MEM_offs;\n"
18496 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
18497 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
18498 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
18499 #if RISCV64_DEBUG_CALL
18500 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
18501 #endif
18502 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
18503 "{\n"
18504  "((RISCV64*)cpu)->RES = 0;\n"
18505  #if RISCV64_DEBUG_CALL
18506  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
18507  #endif
18508 "}\n"
18509 
18510 
18511  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18512 
18513  "return exception;\n"
18514 ;
18515 return true;
18516 },
18517 0,
18518 nullptr
18519 );
18520 //-------------------------------------------------------------------------------------------------------------------
18521 
18522 
fmsub_d_rd_frs1_frs2_frs3
static InstructionDefinition fmsub_d_rd_frs1_frs2_frs3(ISA32_RISCV64, "fmsub.d",(uint32_t) 0x2000047,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmsub.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs3)+"] & 0xffffffffffffffff), (etiss_uint32)1, choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amomin_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomin_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomin.d",(uint32_t) 0x8000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomin.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = res1; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "if((etiss_int64)cast_2 > (etiss_int64)cast_1)\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
csrrw_rd_csr_rs1
static InstructionDefinition csrrw_rd_csr_rs1(ISA32_RISCV64, "csrrw",(uint32_t) 0x1073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_uint64 rs_val = 0;\n" "etiss_uint64 csr_val = 0;\n" "etiss_int64 writeMaskM = 0;\n" "rs_val = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "csr_val = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = rs_val;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = csr_val;\n" "}\n" "else\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = rs_val;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
lwu_rd_imm_rs1_
static InstructionDefinition lwu_rd_imm_rs1_(ISA32_RISCV64, "lwu",(uint32_t) 0x6003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lwu\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)MEM_offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
subw_
static InstructionDefinition subw_(ISA32_RISCV64, "subw",(uint32_t) 0x4000003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//subw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "res = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) - (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff);\n" "etiss_int32 cast_0 = res; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmv_d_x_rd_rs1
static InstructionDefinition fmv_d_x_rd_rs1(ISA32_RISCV64, "fmv.d.x",(uint32_t) 0xf2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmv.d.x\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fdiv_d_rd_frs1_frs2
static InstructionDefinition fdiv_d_rd_frs1_frs2(ISA32_RISCV64, "fdiv.d",(uint32_t) 0x1a000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fdiv.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fdiv_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
flt_d_rd_frs1_frs2
static InstructionDefinition flt_d_rd_frs1_frs2(ISA32_RISCV64, "flt.d",(uint32_t) 0xa2001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//flt.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)2);\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sb_rs2_imm_rs1_
static InstructionDefinition sb_rs2_imm_rs1_(ISA32_RISCV64, "sb",(uint32_t) 0x23,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sb\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint8 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,1);\n" "if((offs + 1 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
lw_rd_imm_rs1_
static InstructionDefinition lw_rd_imm_rs1_(ISA32_RISCV64, "lw",(uint32_t) 0x2003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_1 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
slt_rd_rs1_rs2
static InstructionDefinition slt_rd_rs1_rs2(ISA32_RISCV64, "slt",(uint32_t) 0x2033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//slt\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 choose1 = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n" "{\n" "choose1 = 1;\n" "}\n" "else\n" "{\n" "choose1 = 0;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = choose1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
ISA32_RISCV64
etiss::instr::InstructionGroup ISA32_RISCV64("ISA32_RISCV64", 32)
fcvt_l_s_rd_frs1
static InstructionDefinition fcvt_l_s_rd_frs1(ISA32_RISCV64, "fcvt.l.s",(uint32_t) 0xc0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.l.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_uint32 flags = 0;\n" "res = fcvt_32_64(unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]), (etiss_uint32)0, ("+toString(rm)+" & 0xff));\n" "etiss_int64 cast_0 = res; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
divu_rd_rs1_rs2
static InstructionDefinition divu_rd_rs1_rs2(ISA32_RISCV64, "divu",(uint32_t) 0x2005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//divu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] / *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = - 1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fsqrt_d_rd_frs1
static InstructionDefinition fsqrt_d_rd_frs1(ISA32_RISCV64, "fsqrt.d",(uint32_t) 0x5a000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsqrt.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fsqrt_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sc_w_rd_rs1_rs2
static InstructionDefinition sc_w_rd_rs1_rs2(ISA32_RISCV64, "sc.w",(uint32_t) 0x1800202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sc.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if(offs == ((RISCV64*)cpu)->RES)\n" "{\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 0;\n" "}\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "else\n" "{\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 1;\n" "}\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fadd_d_rd_frs1_frs2
static InstructionDefinition fadd_d_rd_frs1_frs2(ISA32_RISCV64, "fadd.d",(uint32_t) 0x2000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fadd.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sd_rs2_imm_rs1_
static InstructionDefinition sd_rs2_imm_rs1_(ISA32_RISCV64, "sd",(uint32_t) 0x3023,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sd\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:436
sltu_rd_rs1_rs2
static InstructionDefinition sltu_rd_rs1_rs2(ISA32_RISCV64, "sltu",(uint32_t) 0x3033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sltu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 choose1 = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"] < (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = 1;\n" "}\n" "else\n" "{\n" "choose1 = 0;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = choose1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64MMU
Definition: RISCV64MMU.h:56
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
add_rd_rs1_rs2
static InstructionDefinition add_rd_rs1_rs2(ISA32_RISCV64, "add",(uint32_t) 0x33,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//add\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs1)+"] + *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
srai_rd_rs1_shamt
static InstructionDefinition srai_rd_rs1_shamt(ISA32_RISCV64, "srai",(uint32_t) 0x40005013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(25, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srai\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 >> "+toString(shamt)+");\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
endif
endif() endforeach() unset(LOCAL_SOURCE1) unset(LOCAL_SOURCE2) set(ETISS_HEADER $
Definition: CMakeLists.txt:42
slliw_rd_rs1_shamt
static InstructionDefinition slliw_rd_rs1_shamt(ISA32_RISCV64, "slliw",(uint32_t) 0x101b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(24, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//slliw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "sh_val = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) << "+toString(shamt)+");\n" "etiss_int32 cast_0 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::S7
etiss_uint64 S7
Definition: RISCV64.h:66
c_addi_rs1_imm
static InstructionDefinition c_addi_rs1_imm(ISA16_RISCV64, "c.addi",(uint16_t) 0x1,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(12, 12);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(6, 2);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294967232;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rs1)+"] = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
div_rd_rs1_rs2
static InstructionDefinition div_rd_rs1_rs2(ISA32_RISCV64, "div",(uint32_t) 0x2004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//div\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 XLM1 = 0;\n" "etiss_int64 MMIN = 0;\n" "etiss_int64 M1 = 0;\n" "etiss_int64 ONE = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "M1 = - 1;\n" "XLM1 = 64 - 1;\n" "ONE = 1;\n" "MMIN = (ONE << XLM1);\n" "if((*((RISCV64*)cpu)->X["+toString(rs1)+"] == MMIN) && (*((RISCV64*)cpu)->X["+toString(rs2)+"] == M1))\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = MMIN;\n" "}\n" "else\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_1 / (etiss_int64)cast_0);\n" "}\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = - 1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64_Pipeline2
#define RISCV64_Pipeline2
Definition: RISCV64Arch.cpp:40
etiss::mm::NOERROR
const MM_EXPORT int32_t NOERROR
RISCV64::T1
etiss_uint64 T1
Definition: RISCV64.h:49
c_addiw_rs1_imm
static InstructionDefinition c_addiw_rs1_imm(ISA16_RISCV64, "c.addiw",(uint16_t) 0x2001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(12, 12);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(6, 2);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addiw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int32 res = 0;\n" "if(("+toString(imm)+" & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294967232;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rs1)+" != 0)\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int32)cast_0 + imm_extended;\n" "etiss_int32 cast_1 = res; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rs1)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
ecall_
static InstructionDefinition ecall_(ISA32_RISCV64, "ecall",(uint32_t) 0x73,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//ecall\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "exception = ETISS_RETURNCODE_SYSCALL; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
c_addi16sp_imm
static InstructionDefinition c_addi16sp_imm(ISA16_RISCV64, "c.addi16sp",(uint16_t) 0x6101,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_int64 imm=0;static BitArrayRange R_imm_9(12, 12);etiss_int64 imm_9=R_imm_9.read(ba);imm+=imm_9<< 9;static BitArrayRange R_imm_4(6, 6);etiss_int64 imm_4=R_imm_4.read(ba);imm+=imm_4<< 4;static BitArrayRange R_imm_6(5, 5);etiss_int64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_7(4, 3);etiss_int64 imm_7=R_imm_7.read(ba);imm+=imm_7<< 7;static BitArrayRange R_imm_5(2, 2);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addi16sp\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x200)>>9 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294966272;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[2]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X[2] = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_s_rd_frs1
static InstructionDefinition fcvt_d_s_rd_frs1(ISA32_RISCV64, "fcvt.d.s",(uint32_t) 0x42000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fconv_f2d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffff), ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::gdbcore_
RISCV64GDBCore gdbcore_
Definition: RISCV64Arch.h:147
mret_
static InstructionDefinition mret_(ISA32_RISCV64, "mret",(uint32_t) 0x30200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mret\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->CSR[3088] = (((RISCV64*)cpu)->CSR[768] & 0x1800)>>11;\n" "((RISCV64*)cpu)->CSR[768] ^= (((RISCV64*)cpu)->CSR[768] & 0x1800);\n" "((RISCV64*)cpu)->CSR[768] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[768] & 0x80)>>4)) ^ (((RISCV64*)cpu)->CSR[768] & 0x8);\n" "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[833];\n" "((RISCV64*)cpu)->CSR[0]= ((RISCV64*)cpu)->CSR[768];\n" "((RISCV64*)cpu)->CSR[256]=((RISCV64*)cpu)->CSR[768];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
c_ldsp_rd_uimm_sp_
static InstructionDefinition c_ldsp_rd_uimm_sp_(ISA16_RISCV64, "c.ldsp",(uint16_t) 0x6002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 uimm=0;static BitArrayRange R_uimm_5(12, 12);etiss_uint64 uimm_5=R_uimm_5.read(ba);uimm+=uimm_5<< 5;static BitArrayRange R_uimm_3(6, 5);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(4, 2);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.ldsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:84
slti_rd_rs1_imm
static InstructionDefinition slti_rd_rs1_imm(ISA32_RISCV64, "slti",(uint32_t) 0x2013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//slti\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int8 choose1 = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = imm_extended; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n" "{\n" "choose1 = 1;\n" "}\n" "else\n" "{\n" "choose1 = 0;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = choose1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
xori_rd_rs1_imm
static InstructionDefinition xori_rd_rs1_imm(ISA32_RISCV64, "xori",(uint32_t) 0x4013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//xori\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 ^ imm_extended);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
bne_rs1_rs2_imm
static InstructionDefinition bne_rs1_rs2_imm(ISA32_RISCV64, "bne",(uint32_t) 0x1063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//bne\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+"] != *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::A6
etiss_uint64 A6
Definition: RISCV64.h:59
RISCV64::A1
etiss_uint64 A1
Definition: RISCV64.h:54
fcvt_s_lu_rd_xrs1
static InstructionDefinition fcvt_s_lu_rd_xrs1(ISA32_RISCV64, "fcvt.s.lu",(uint32_t) 0xd0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.lu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fcvt_64_32(*((RISCV64*)cpu)->X["+toString(rs1)+"], (etiss_uint32)3);\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fnmsub_s_rd_frs1_frs2_frs3
static InstructionDefinition fnmsub_s_rd_frs1_frs2_frs3(ISA32_RISCV64, "fnmsub.s",(uint32_t) 0x4b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fnmsub.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], ((RISCV64*)cpu)->F["+toString(rs3)+"], (etiss_uint32)3, choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "frs3 = unbox_s(((RISCV64*)cpu)->F["+toString(rs3)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)3, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_addw_8_rd_8_rd_8_rs2
static InstructionDefinition c_addw_8_rd_8_rd_8_rs2(ISA16_RISCV64, "c.addw",(uint16_t) 0x9c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "res = (*((RISCV64*)cpu)->X["+toString(rd)+" + 8] & 0xffffffff) + (*((RISCV64*)cpu)->X["+toString(rs2)+" + 8] & 0xffffffff);\n" "etiss_int32 cast_0 = res; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:538
lr_w_rd_rs1
static InstructionDefinition lr_w_rd_rs1(ISA32_RISCV64, "lr.w",(uint32_t) 0x1000202f,(uint32_t) 0xf9f0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lr.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "((RISCV64*)cpu)->RES = offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoxor_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoxor_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoxor.d",(uint32_t) 0x2000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoxor.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "res2 = (res ^ *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
xor_rd_rs1_rs2
static InstructionDefinition xor_rd_rs1_rs2(ISA32_RISCV64, "xor",(uint32_t) 0x4033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//xor\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] ^ *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
csrrwi_rd_csr_zimm
static InstructionDefinition csrrwi_rd_csr_zimm(ISA32_RISCV64, "csrrwi",(uint32_t) 0x5073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;etiss_uint64 zimm=0;static BitArrayRange R_zimm_0(19, 15);etiss_uint64 zimm_0=R_zimm_0.read(ba);zimm+=zimm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrwi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_int64 writeMaskM = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "}\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((etiss_uint64)"+toString(zimm)+" & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (etiss_uint64)"+toString(zimm)+";\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_li_rd_imm
static InstructionDefinition c_li_rd_imm(ISA16_RISCV64, "c.li",(uint16_t) 0x4001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(12, 12);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(6, 2);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.li\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294967232;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
mulhu_rd_rs1_rs2
static InstructionDefinition mulhu_rd_rs1_rs2(ISA32_RISCV64, "mulhu",(uint32_t) 0x2003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mulhu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "res = ((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"] * (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)(res >> 64);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_wu_d_rd_frs1
static InstructionDefinition fcvt_wu_d_rd_frs1(ISA32_RISCV64, "fcvt.wu.d",(uint32_t) 0xc2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.wu.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_int32 cast_0 = fcvt_64_32((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (etiss_uint32)1, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::deleteTimer
void deleteTimer(etiss::Plugin *timer)
delete timer instance
Definition: RISCV64Arch.cpp:240
c_beqz_8_rs1_imm
static InstructionDefinition c_beqz_8_rs1_imm(ISA16_RISCV64, "c.beqz",(uint16_t) 0xc001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_8(12, 12);etiss_int64 imm_8=R_imm_8.read(ba);imm+=imm_8<< 8;static BitArrayRange R_imm_3(11, 10);etiss_int64 imm_3=R_imm_3.read(ba);imm+=imm_3<< 3;static BitArrayRange R_imm_6(6, 5);etiss_int64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_1(4, 3);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_5(2, 2);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.beqz\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x100)>>8 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294966784;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+" + 8] == 0)\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 2;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
c_sw_8_rs2_uimm_8_rs1_
static InstructionDefinition c_sw_8_rs2_uimm_8_rs1_(ISA16_RISCV64, "c.sw",(uint16_t) 0xc000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_2(6, 6);etiss_uint64 uimm_2=R_uimm_2.read(ba);uimm+=uimm_2<< 2;static BitArrayRange R_uimm_6(5, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.sw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+" + 8];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
jal_rd_imm
static InstructionDefinition jal_rd_imm(ISA32_RISCV64, "jal",(uint32_t) 0x6f,(uint32_t) 0x7f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_20(31, 31);etiss_int64 imm_20=R_imm_20.read(ba);imm+=imm_20<< 20;static BitArrayRange R_imm_1(30, 21);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(20, 20);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;static BitArrayRange R_imm_12(19, 12);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//jal\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x100000)>>20 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4292870144;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "else\n" "{\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "cpu->instructionPointer = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
and_rd_rs1_rs2
static InstructionDefinition and_rd_rs1_rs2(ISA32_RISCV64, "and",(uint32_t) 0x7033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//and\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::listenerSupportedRegisters_
std::set< std::string > listenerSupportedRegisters_
Definition: RISCV64Arch.h:145
fsgnj_s_rd_frs1_frs2
static InstructionDefinition fsgnj_s_rd_frs1_frs2(ISA32_RISCV64, "fsgnj.s",(uint32_t) 0x20000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnj.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((((RISCV64*)cpu)->F["+toString(rs1)+"] & 2147483647) | (((RISCV64*)cpu)->F["+toString(rs2)+"] & -2147483648));\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = ((frs1 & 2147483647) | (frs2 & -2147483648));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_or_8_rd_8_rs2
static InstructionDefinition c_or_8_rd_8_rs2(ISA16_RISCV64, "c.or",(uint16_t) 0x8c41,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.or\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rd_idx = 0;\n" "rd_idx = "+toString(rd)+" + 8;\n" "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] | *((RISCV64*)cpu)->X["+toString(rs2)+" + 8]);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
c_ebreak_
static InstructionDefinition c_ebreak_(ISA16_RISCV64, "c.ebreak",(uint16_t) 0x9002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.ebreak\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "return ETISS_RETURNCODE_CPUFINISHED; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
srliw_rd_rs1_shamt
static InstructionDefinition srliw_rd_rs1_shamt(ISA32_RISCV64, "srliw",(uint32_t) 0x501b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(24, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srliw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "sh_val = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) >> "+toString(shamt)+");\n" "etiss_int32 cast_0 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::RISCV64Arch
RISCV64Arch()
Definition: RISCV64Arch.cpp:50
RISCV64::SP
etiss_uint64 SP
Definition: RISCV64.h:45
c_bnez_8_rs1_imm
static InstructionDefinition c_bnez_8_rs1_imm(ISA16_RISCV64, "c.bnez",(uint16_t) 0xe001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_8(12, 12);etiss_int64 imm_8=R_imm_8.read(ba);imm+=imm_8<< 8;static BitArrayRange R_imm_3(11, 10);etiss_int64 imm_3=R_imm_3.read(ba);imm+=imm_3<< 3;static BitArrayRange R_imm_6(6, 5);etiss_int64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_1(4, 3);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_5(2, 2);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.bnez\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x100)>>8 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294966784;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+" + 8] != 0)\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 2;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
c_lwsp_rd_sp_uimm
static InstructionDefinition c_lwsp_rd_sp_uimm(ISA16_RISCV64, "c.lwsp",(uint16_t) 0x4002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 uimm=0;static BitArrayRange R_uimm_5(12, 12);etiss_uint64 uimm_5=R_uimm_5.read(ba);uimm+=uimm_5<< 5;static BitArrayRange R_uimm_2(6, 4);etiss_uint64 uimm_2=R_uimm_2.read(ba);uimm+=uimm_2<< 2;static BitArrayRange R_uimm_6(3, 2);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.lwsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::plugin::gdb::GDBCore
provides to architecture dependent registers as defined by gdb
Definition: GDBCore.h:76
fsgnjx_s_rd_frs1_frs2
static InstructionDefinition fsgnjx_s_rd_frs1_frs2(ISA32_RISCV64, "fsgnjx.s",(uint32_t) 0x20002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnjx.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = (((RISCV64*)cpu)->F["+toString(rs1)+"] ^ (((RISCV64*)cpu)->F["+toString(rs2)+"] & -2147483648));\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = (frs1 ^ (frs2 & -2147483648));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::newCPU
virtual ETISS_CPU * newCPU()
allocate new cpu structure
Definition: RISCV64Arch.cpp:60
auipc_rd_imm
static InstructionDefinition auipc_rd_imm(ISA32_RISCV64, "auipc",(uint32_t) 0x17,(uint32_t) 0x7f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 12);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//auipc\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x80000000)>>31 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0 + imm_extended;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::TP
etiss_uint64 TP
Definition: RISCV64.h:47
fcvt_s_l_rd_xrs1
static InstructionDefinition fcvt_s_l_rd_xrs1(ISA32_RISCV64, "fcvt.s.l",(uint32_t) 0xd0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.l\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fcvt_64_32(*((RISCV64*)cpu)->X["+toString(rs1)+"], (etiss_uint32)2);\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_l_d_rd_frs1
static InstructionDefinition fcvt_l_d_rd_frs1(ISA32_RISCV64, "fcvt.l.d",(uint32_t) 0xc2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.l.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_int64 cast_0 = fcvt_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (etiss_uint32)0, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_lw_8_rd_uimm_8_rs1_
static InstructionDefinition c_lw_8_rd_uimm_8_rs1_(ISA16_RISCV64, "c.lw",(uint16_t) 0x4000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_2(6, 6);etiss_uint64 uimm_2=R_uimm_2.read(ba);uimm+=uimm_2<< 2;static BitArrayRange R_uimm_6(5, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(4, 2);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.lw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
remuw_rd_rs1_rs2
static InstructionDefinition remuw_rd_rs1_rs2(ISA32_RISCV64, "remuw",(uint32_t) 0x200703b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//remuw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) != 0)\n" "{\n" "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) % (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "else\n" "{\n" "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sc_d_rd_rs1_rs2
static InstructionDefinition sc_d_rd_rs1_rs2(ISA32_RISCV64, "sc.d",(uint32_t) 0x1800302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sc.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if(offs == ((RISCV64*)cpu)->RES)\n" "{\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 0;\n" "}\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "else\n" "{\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 1;\n" "}\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fmul_s_rd_frs1_frs2
static InstructionDefinition fmul_s_rd_frs1_frs2(ISA32_RISCV64, "fmul.s",(uint32_t) 0x10000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmul.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmul_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmul_s(frs1, frs2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_mv_rd_rs2
static InstructionDefinition c_mv_rd_rs2(ISA16_RISCV64, "c.mv",(uint16_t) 0x8002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.mv\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
sllw_rd_rs1_rs2
static InstructionDefinition sllw_rd_rs1_rs2(ISA32_RISCV64, "sllw",(uint32_t) 0x103b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sllw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "etiss_uint32 count = 0;\n" "etiss_int32 mask = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "mask = 31;\n" "count = ((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) & mask);\n" "sh_val = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) << count);\n" "etiss_int32 cast_0 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::RES
etiss_uint64 RES
Definition: RISCV64.h:81
remu_rd_rs1_rs2
static InstructionDefinition remu_rd_rs1_rs2(ISA32_RISCV64, "remu",(uint32_t) 0x2007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//remu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] % *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition: CPU.h:88
amoadd_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoadd_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoadd.d",(uint32_t) 0x302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoadd.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "res2 = res + *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fnmadd_s_rd_frs1_frs2_frs3
static InstructionDefinition fnmadd_s_rd_frs1_frs2_frs3(ISA32_RISCV64, "fnmadd.s",(uint32_t) 0x4f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fnmadd.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], ((RISCV64*)cpu)->F["+toString(rs3)+"], (etiss_uint32)2, choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "frs3 = unbox_s(((RISCV64*)cpu)->F["+toString(rs3)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:568
fnmadd_d_rd_frs1_frs2_frs3
static InstructionDefinition fnmadd_d_rd_frs1_frs2_frs3(ISA32_RISCV64, "fnmadd.d",(uint32_t) 0x200004f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fnmadd.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs3)+"] & 0xffffffffffffffff), (etiss_uint32)2, choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::GP
etiss_uint64 GP
Definition: RISCV64.h:46
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:385
rd
static BitArrayRange rd(25, 21)
RISCV64::ZERO
etiss_uint64 ZERO
Definition: RISCV64.h:43
RISCV64::A0
etiss_uint64 A0
Definition: RISCV64.h:53
jalr_rd_rs1_imm
static InstructionDefinition jalr_rd_rs1_imm(ISA32_RISCV64, "jalr",(uint32_t) 0x67,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//jalr\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 new_pc = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "new_pc = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "else\n" "{\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "cpu->instructionPointer = (new_pc & ~1)&0xffffffffffffffff;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
sraiw_rd_rs1_shamt
static InstructionDefinition sraiw_rd_rs1_shamt(ISA32_RISCV64, "sraiw",(uint32_t) 0x4000501b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(24, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sraiw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int32 sh_val = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "sh_val = ((etiss_int32)cast_0 >> "+toString(shamt)+");\n" "etiss_int32 cast_1 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_w_s_rd_frs1
static InstructionDefinition fcvt_w_s_rd_frs1(ISA32_RISCV64, "fcvt.w.s",(uint32_t) 0xc0000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.w.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "if(64 == 32)\n" "{\n" "etiss_int32 cast_0 = fcvt_s(((RISCV64*)cpu)->F["+toString(rs1)+"], (etiss_uint32)0, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)0, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_wu_s_rd_frs1
static InstructionDefinition fcvt_wu_s_rd_frs1(ISA32_RISCV64, "fcvt.wu.s",(uint32_t) 0xc0100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.wu.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "if(64 == 32)\n" "{\n" "etiss_int32 cast_0 = fcvt_s(((RISCV64*)cpu)->F["+toString(rs1)+"], (etiss_uint32)1, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)1, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
ETISS_CPU::resourceUsages
etiss_uint64 resourceUsages[ETISS_MAX_RESOURCES]
how many cycles each resource is used
Definition: CPU.h:97
fsqrt_s_rd_frs1
static InstructionDefinition fsqrt_s_rd_frs1(ISA32_RISCV64, "fsqrt.s",(uint32_t) 0x58000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsqrt.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fsqrt_s(((RISCV64*)cpu)->F["+toString(rs1)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fsqrt_s(frs1, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::deleteCPU
virtual void deleteCPU(ETISS_CPU *)
delete cpu structure
Definition: RISCV64Arch.cpp:194
fence_i_
static InstructionDefinition fence_i_(ISA32_RISCV64, "fence_i",(uint32_t) 0x100f,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_uint64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fence_i\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->FENCE[1] = "+toString(imm)+";\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::ins_X
etiss_uint64 ins_X[32]
Definition: RISCV64.h:76
RISCV64::S1
etiss_uint64 S1
Definition: RISCV64.h:52
fclass_d_rd_frs1
static InstructionDefinition fclass_d_rd_frs1(ISA32_RISCV64, "fclass.d",(uint32_t) 0xe2001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fclass.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = fclass_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff));\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::FCSR
etiss_uint32 FCSR
Definition: RISCV64.h:78
ETISS_CPU::mode
etiss_uint32 mode
instruction set mode of the processor
Definition: CPU.h:107
lui_rd_imm
static InstructionDefinition lui_rd_imm(ISA32_RISCV64, "lui",(uint32_t) 0x37,(uint32_t) 0x7f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 12);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lui\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x80000000)>>31 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = imm_extended;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amomaxu_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomaxu_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomaxu.d",(uint32_t) 0xe000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomaxu.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "if(res1 < *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64ArchSpecificImp.h
etiss::instr::BitArrayRange
Acts as a view/filter to a BitArray.
Definition: Instruction.h:337
RISCV64::A3
etiss_uint64 A3
Definition: RISCV64.h:56
srl_rd_rs1_rs2
static InstructionDefinition srl_rd_rs1_rs2(ISA32_RISCV64, "srl",(uint32_t) 0x5033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srl\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] >> (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 64 - 1));\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amominu.w",(uint32_t) 0xc000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amominu.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "if(res1 > *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
c_srai_8_rs1_shamt
static InstructionDefinition c_srai_8_rs1_shamt(ISA16_RISCV64, "c.srai",(uint16_t) 0x8401,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_5(12, 12);etiss_uint64 shamt_5=R_shamt_5.read(ba);shamt+=shamt_5<< 5;static BitArrayRange R_shamt_0(6, 2);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.srai\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rs1_idx = 0;\n" "rs1_idx = "+toString(rs1)+" + 8;\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[rs1_idx]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X[rs1_idx] = ((etiss_int64)cast_0 >> "+toString(shamt)+");\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::getGDBCore
virtual etiss::plugin::gdb::GDBCore & getGDBCore()
get the GDBcore for RISCV64 architecture
Definition: RISCV64Arch.cpp:227
c_fsdsp_rs2_uimm_x2_
static InstructionDefinition c_fsdsp_rs2_uimm_x2_(ISA16_RISCV64, "c.fsdsp",(uint16_t) 0xa002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(9, 7);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.fsdsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
sfence_vma_
static InstructionDefinition sfence_vma_(ISA32_RISCV64, "sfence.vma",(uint32_t) 0x12000073,(uint32_t) 0xfe007fff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[3], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sfence.vma\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->FENCE[2] = "+toString(rs1)+";\n" "((RISCV64*)cpu)->FENCE[3] = "+toString(rs2)+";\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
divw_rd_rs1_rs2
static InstructionDefinition divw_rd_rs1_rs2(ISA32_RISCV64, "divw",(uint32_t) 0x200403b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//divw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int32 MMIN = 0;\n" "etiss_int32 M1 = 0;\n" "etiss_int32 ONE = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "M1 = - 1;\n" "ONE = 1;\n" "MMIN = (ONE << 31);\n" "if(((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) == MMIN) && ((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) == M1))\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ( - 1 << 31);\n" "}\n" "else\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = ((etiss_int64)cast_1 / (etiss_int64)cast_0); \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_2;\n" "}\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = - 1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmsub_s_rd_frs1_frs2_frs3
static InstructionDefinition fmsub_s_rd_frs1_frs2_frs3(ISA32_RISCV64, "fmsub.s",(uint32_t) 0x47,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmsub.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], ((RISCV64*)cpu)->F["+toString(rs3)+"], (etiss_uint32)1, choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "frs3 = unbox_s(((RISCV64*)cpu)->F["+toString(rs3)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)1, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_l_rd_rs1
static InstructionDefinition fcvt_d_l_rd_rs1(ISA32_RISCV64, "fcvt.d.l",(uint32_t) 0xd2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.l\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = fcvt_d((etiss_int64)cast_0, (etiss_uint32)2, ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_swsp_rs2_uimm_sp_
static InstructionDefinition c_swsp_rs2_uimm_sp_(ISA16_RISCV64, "c.swsp",(uint16_t) 0xc002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_2(12, 9);etiss_uint64 uimm_2=R_uimm_2.read(ba);uimm+=uimm_2<< 2;static BitArrayRange R_uimm_6(8, 7);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.swsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ETISS_CPU::instructionPointer
etiss_uint64 instructionPointer
pointer to next instruction.
Definition: CPU.h:92
addi_rd_rs1_imm
static InstructionDefinition addi_rd_rs1_imm(ISA32_RISCV64, "addi",(uint32_t) 0x13,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//addi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0 + imm_extended;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::mm::MMU
Definition: MMU.h:75
sub_rd_rs1_rs2
static InstructionDefinition sub_rd_rs1_rs2(ISA32_RISCV64, "sub",(uint32_t) 0x40000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sub\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs1)+"] - *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
srlw_rd_rs1_rs2
static InstructionDefinition srlw_rd_rs1_rs2(ISA32_RISCV64, "srlw",(uint32_t) 0x503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srlw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "etiss_uint32 count = 0;\n" "etiss_int32 mask = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "mask = 31;\n" "count = ((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) & mask);\n" "sh_val = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) >> count);\n" "etiss_int32 cast_0 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_lu_rd_rs1
static InstructionDefinition fcvt_d_lu_rd_rs1(ISA32_RISCV64, "fcvt.d.lu",(uint32_t) 0xd2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.lu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fcvt_d((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"], (etiss_uint32)3, ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
tlb_overlap_handler
int32_t tlb_overlap_handler(int32_t fault, MMU *mmu, uint64_t vma, MM_ACCESS access)
Definition: RISCV64Arch.cpp:45
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:52
fmax_s_rd_frs1_frs2
static InstructionDefinition fmax_s_rd_frs1_frs2(ISA32_RISCV64, "fmax.s",(uint32_t) 0x28001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmax.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fsel_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = fsel_s(frs1, frs2, (etiss_uint32)1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::CPUArch
the interface to translate instructions of and processor architecture
Definition: CPUArch.h:157
RISCV64::T2
etiss_uint64 T2
Definition: RISCV64.h:50
reg_name
static const char *const reg_name[]
Definition: RISCV64Arch.cpp:251
fcvt_s_w_rd_rs1
static InstructionDefinition fcvt_s_w_rd_rs1(ISA32_RISCV64, "fcvt.s.w",(uint32_t) 0xd0000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.w\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fcvt_s((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)2, ("+toString(rm)+" & 0xff));\n" "}\n" "else\n" "{\n" "res = fcvt_s((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)2, ("+toString(rm)+" & 0xff));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::F
etiss_uint64 F[32]
Definition: RISCV64.h:77
amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomaxu.w",(uint32_t) 0xe000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomaxu.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "if(res1 < *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
csrrci_rd_csr_zimm
static InstructionDefinition csrrci_rd_csr_zimm(ISA32_RISCV64, "csrrci",(uint32_t) 0x7073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;etiss_uint64 zimm=0;static BitArrayRange R_zimm_0(19, 15);etiss_uint64 zimm_0=R_zimm_0.read(ba);zimm+=zimm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrci\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_int64 writeMaskM = 0;\n" "res = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "if("+toString(zimm)+" != 0)\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((res & ~(etiss_uint64)"+toString(zimm)+") & writeMask))&0xffffffffffffffff&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (res & ~(etiss_uint64)"+toString(zimm)+")&0xffffffffffffffff;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::instr::InstructionDefinition
maps to Instruction
Definition: Instruction.h:961
csrrsi_rd_csr_zimm
static InstructionDefinition csrrsi_rd_csr_zimm(ISA32_RISCV64, "csrrsi",(uint32_t) 0x6073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;etiss_uint64 zimm=0;static BitArrayRange R_zimm_0(19, 15);etiss_uint64 zimm_0=R_zimm_0.read(ba);zimm+=zimm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrsi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_int64 writeMaskM = 0;\n" "res = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "if("+toString(zimm)+" != 0)\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((res | (etiss_uint64)"+toString(zimm)+") & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (res | (etiss_uint64)"+toString(zimm)+");\n" "}\n" "}\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_jalr_rs1
static InstructionDefinition c_jalr_rs1(ISA16_RISCV64, "c.jalr",(uint16_t) 0x9002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.jalr\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X[1] = "+toString((uint64_t) ic.current_address_)+"ULL + 2;\n" "cpu->instructionPointer = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
addiw_rd_rs1_imm
static InstructionDefinition addiw_rd_rs1_imm(ISA32_RISCV64, "addiw",(uint32_t) 0x1b,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//addiw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int32 res = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int32)cast_0 + imm_extended;\n" "etiss_int32 cast_1 = res; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sll_rd_rs1_rs2
static InstructionDefinition sll_rd_rs1_rs2(ISA32_RISCV64, "sll",(uint32_t) 0x1033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sll\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] << (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 64 - 1));\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amoor_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoor_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoor.w",(uint32_t) 0x4000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoor.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "res2 = (res1 | *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
sltiu_rd_rs1_imm
static InstructionDefinition sltiu_rd_rs1_imm(ISA32_RISCV64, "sltiu",(uint32_t) 0x3013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sltiu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 full_imm = 0;\n" "etiss_int8 choose1 = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = imm_extended; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "full_imm = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"] < (etiss_uint64)full_imm)\n" "{\n" "choose1 = 1;\n" "}\n" "else\n" "{\n" "choose1 = 0;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = choose1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_sub_8_rd_8_rs2
static InstructionDefinition c_sub_8_rd_8_rs2(ISA16_RISCV64, "c.sub",(uint16_t) 0x8c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.sub\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rd_idx = 0;\n" "rd_idx = "+toString(rd)+" + 8;\n" "*((RISCV64*)cpu)->X[rd_idx] = *((RISCV64*)cpu)->X[rd_idx] - *((RISCV64*)cpu)->X["+toString(rs2)+" + 8];\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
fmv_w_x_rd_rs1
static InstructionDefinition fmv_w_x_rd_rs1(ISA32_RISCV64, "fmv.w.x",(uint32_t) 0xf0000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmv.w.x\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 upper = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff);\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)(*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff));\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amominu_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amominu_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amominu.d",(uint32_t) 0xc000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amominu.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "if(res > *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64_Pipeline1
#define RISCV64_Pipeline1
Definition: RISCV64Arch.cpp:39
RISCV64Arch::getInstructionSizeInBytes
virtual unsigned getInstructionSizeInBytes()
Definition: RISCV64Arch.cpp:210
RISCV64Arch::getListenerSupportedRegisters
virtual const std::set< std::string > & getListenerSupportedRegisters()
Definition: RISCV64Arch.cpp:55
RISCV64::S9
etiss_uint64 S9
Definition: RISCV64.h:68
fadd_s_rd_frs1_frs2
static InstructionDefinition fadd_s_rd_frs1_frs2(ISA32_RISCV64, "fadd.s",(uint32_t) 0x53,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fadd.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fadd_s(frs1, frs2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
feq_d_rd_frs1_frs2
static InstructionDefinition feq_d_rd_frs1_frs2(ISA32_RISCV64, "feq.d",(uint32_t) 0xa2002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//feq.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)0);\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmin_s_rd_frs1_frs2
static InstructionDefinition fmin_s_rd_frs1_frs2(ISA32_RISCV64, "fmin.s",(uint32_t) 0x28000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmin.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fsel_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)0);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = fsel_s(frs1, frs2, (etiss_uint32)0);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fdiv_s_rd_frs1_frs2
static InstructionDefinition fdiv_s_rd_frs1_frs2(ISA32_RISCV64, "fdiv.s",(uint32_t) 0x18000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fdiv.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fdiv_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fdiv_s(frs1, frs2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
slli_rd_rs1_shamt
static InstructionDefinition slli_rd_rs1_shamt(ISA32_RISCV64, "slli",(uint32_t) 0x1013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(25, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//slli\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] << "+toString(shamt)+");\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_w_rd_rs1
static InstructionDefinition fcvt_d_w_rd_rs1(ISA32_RISCV64, "fcvt.d.w",(uint32_t) 0xd2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.w\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = fcvt_32_64((etiss_int64)cast_0, (etiss_uint32)2, ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_wu_rd_rs1
static InstructionDefinition fcvt_d_wu_rd_rs1(ISA32_RISCV64, "fcvt.d.wu",(uint32_t) 0xd2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.wu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fcvt_32_64((etiss_uint64)(*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)3, ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmadd_s_rd_frs1_frs2_frs3
static InstructionDefinition fmadd_s_rd_frs1_frs2_frs3(ISA32_RISCV64, "fmadd.s",(uint32_t) 0x43,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmadd.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], ((RISCV64*)cpu)->F["+toString(rs3)+"], (etiss_uint32)0, choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "frs3 = unbox_s(((RISCV64*)cpu)->F["+toString(rs3)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)0, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amoor_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoor_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoor.d",(uint32_t) 0x4000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoor.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "res2 = (res | *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
mul_rd_rs1_rs2
static InstructionDefinition mul_rd_rs1_rs2(ISA32_RISCV64, "mul",(uint32_t) 0x2000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mul\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "res = ((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"] * (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)res;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
uret_
static InstructionDefinition uret_(ISA32_RISCV64, "uret",(uint32_t) 0x200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//uret\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->CSR[3088] = 0;\n" "((RISCV64*)cpu)->CSR[0] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[0] & 0x10)>>4)) ^ (((RISCV64*)cpu)->CSR[0] & 0x1);\n" "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[65];\n" "((RISCV64*)cpu)->CSR[768]= ((RISCV64*)cpu)->CSR[0];\n" "((RISCV64*)cpu)->CSR[256]=((RISCV64*)cpu)->CSR[0];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
fence_
static InstructionDefinition fence_(ISA32_RISCV64, "fence",(uint32_t) 0xf,(uint32_t) 0xf000707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 succ=0;static BitArrayRange R_succ_0(23, 20);etiss_uint64 succ_0=R_succ_0.read(ba);succ+=succ_0;etiss_uint64 pred=0;static BitArrayRange R_pred_0(27, 24);etiss_uint64 pred_0=R_pred_0.read(ba);pred+=pred_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[0], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fence\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->FENCE[0] = (("+toString(pred)+" << 4) | "+toString(succ)+");\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_add_rd_rs2
static InstructionDefinition c_add_rd_rs2(ISA16_RISCV64, "c.add",(uint16_t) 0x9002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rd], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.add\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rd)+"] + *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
fsgnjn_d_rd_frs1_frs2
static InstructionDefinition fsgnjn_d_rd_frs1_frs2(ISA32_RISCV64, "fsgnjn.d",(uint32_t) 0x22001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnjn.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 ONE = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 MSK1 = 0;\n" "etiss_int64 MSK2 = 0;\n" "ONE = 1;\n" "MSK1 = (ONE << 63);\n" "MSK2 = MSK1 - 1;\n" "res = (((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff) & MSK2) | (~(((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff) & MSK1))&0xffffffffffffffff;\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fnmsub_d_rd_frs1_frs2_frs3
static InstructionDefinition fnmsub_d_rd_frs1_frs2_frs3(ISA32_RISCV64, "fnmsub.d",(uint32_t) 0x200004b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fnmsub.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs3)+"] & 0xffffffffffffffff), (etiss_uint32)3, choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
rem_rd_rs1_rs2
static InstructionDefinition rem_rd_rs1_rs2(ISA32_RISCV64, "rem",(uint32_t) 0x2006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//rem\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int32 XLM1 = 0;\n" "etiss_int64 MMIN = 0;\n" "etiss_int64 M1 = 0;\n" "etiss_int64 ONE = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "M1 = - 1;\n" "XLM1 = 64 - 1;\n" "ONE = 1;\n" "MMIN = (ONE << XLM1);\n" "if((*((RISCV64*)cpu)->X["+toString(rs1)+"] == MMIN) && (*((RISCV64*)cpu)->X["+toString(rs2)+"] == M1))\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 0;\n" "}\n" "else\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_1 % (etiss_int64)cast_0);\n" "}\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::RA
etiss_uint64 RA
Definition: RISCV64.h:44
c_xor_8_rd_8_rs2
static InstructionDefinition c_xor_8_rd_8_rs2(ISA16_RISCV64, "c.xor",(uint16_t) 0x8c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.xor\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rd_idx = 0;\n" "rd_idx = "+toString(rd)+" + 8;\n" "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] ^ *((RISCV64*)cpu)->X["+toString(rs2)+" + 8]);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::CodePart::getRegisterDependencies
RegisterSet & getRegisterDependencies()
Definition: CodePart.h:413
addw_
static InstructionDefinition addw_(ISA32_RISCV64, "addw",(uint32_t) 0x3b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//addw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "res = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) + (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff);\n" "etiss_int32 cast_0 = res; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Timer
Definition: RISCV64Timer.h:66
RISCV64::T4
etiss_uint64 T4
Definition: RISCV64.h:72
fmv_x_w_rd_frs1
static InstructionDefinition fmv_x_w_rd_frs1(ISA32_RISCV64, "fmv.x.w",(uint32_t) 0xe0000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmv.x.w\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 cast_0 = (((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_sdsp_rs2_uimm_sp_
static InstructionDefinition c_sdsp_rs2_uimm_sp_(ISA16_RISCV64, "c.sdsp",(uint16_t) 0xe002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(9, 7);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.sdsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ori_rd_rs1_imm
static InstructionDefinition ori_rd_rs1_imm(ISA32_RISCV64, "ori",(uint32_t) 0x6013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//ori\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 | imm_extended);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
uint32_t
unsigned int uint32_t
Definition: stddef.h:23
fle_s_rd_frs1_frs2
static InstructionDefinition fle_s_rd_frs1_frs2(ISA32_RISCV64, "fle.s",(uint32_t) 0xa0000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fle.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)1);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
flw_rd_imm_xrs1_
static InstructionDefinition flw_rd_imm_xrs1_(ISA32_RISCV64, "flw",(uint32_t) 0x2007,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//flw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "res = MEM_offs;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoand_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoand_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoand.w",(uint32_t) 0x6000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoand.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "res2 = (res1 & *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
remw_rd_rs1_rs2
static InstructionDefinition remw_rd_rs1_rs2(ISA32_RISCV64, "remw",(uint32_t) 0x200603b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//remw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int32 MMIN = 0;\n" "etiss_int32 M1 = 0;\n" "etiss_int32 ONE = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "M1 = - 1;\n" "ONE = 1;\n" "MMIN = (ONE << 31);\n" "if(((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) == MMIN) && (*((RISCV64*)cpu)->X["+toString(rs2)+"] == M1))\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 0;\n" "}\n" "else\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = ((etiss_int64)cast_1 % (etiss_int64)cast_0); \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_2;\n" "}\n" "}\n" "else\n" "{\n" "etiss_int64 cast_3 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_3 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_3 =0x0 + (etiss_uint64)cast_3 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_3;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::S2
etiss_uint64 S2
Definition: RISCV64.h:61
RISCV64::S4
etiss_uint64 S4
Definition: RISCV64.h:63
etiss::toString
std::string toString(const T &val)
conversion of type T to std::string.
Definition: Misc.h:174
c_j_imm
static InstructionDefinition c_j_imm(ISA16_RISCV64, "c.j",(uint16_t) 0xa001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_int64 imm=0;static BitArrayRange R_imm_11(12, 12);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;static BitArrayRange R_imm_4(11, 11);etiss_int64 imm_4=R_imm_4.read(ba);imm+=imm_4<< 4;static BitArrayRange R_imm_8(10, 9);etiss_int64 imm_8=R_imm_8.read(ba);imm+=imm_8<< 8;static BitArrayRange R_imm_10(8, 8);etiss_int64 imm_10=R_imm_10.read(ba);imm+=imm_10<< 10;static BitArrayRange R_imm_6(7, 7);etiss_int64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_7(6, 6);etiss_int64 imm_7=R_imm_7.read(ba);imm+=imm_7<< 7;static BitArrayRange R_imm_1(5, 3);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_5(2, 2);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.j\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "cpu->instructionPointer = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
etiss::CodeBlock::fileglobalCode
std::set< std::string > & fileglobalCode()
Definition: CodePart.h:603
amomax_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomax_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomax.d",(uint32_t) 0xa000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomax.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = res; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "if((etiss_int64)cast_2 < (etiss_int64)cast_1)\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoadd_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoadd_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoadd.w",(uint32_t) 0x202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoadd.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "res2 = res1 + *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64::S8
etiss_uint64 S8
Definition: RISCV64.h:67
c_andi_8_rs1_imm
static InstructionDefinition c_andi_8_rs1_imm(ISA16_RISCV64, "c.andi",(uint16_t) 0x8801,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(12, 12);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(6, 2);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.andi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int8 rs1_idx = 0;\n" "if(("+toString(imm)+" & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294967232;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "rs1_idx = "+toString(rs1)+" + 8;\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[rs1_idx]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X[rs1_idx] = ((etiss_int64)cast_0 & imm_extended);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
RISCV64::A2
etiss_uint64 A2
Definition: RISCV64.h:55
fsub_s_rd_frs1_frs2
static InstructionDefinition fsub_s_rd_frs1_frs2(ISA32_RISCV64, "fsub.s",(uint32_t) 0x8000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsub.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fsub_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fsub_s(frs1, frs2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_s_d_rd_frs1
static InstructionDefinition fcvt_s_d_rd_frs1(ISA32_RISCV64, "fcvt.s.d",(uint32_t) 0x40100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fconv_d2f(((RISCV64*)cpu)->F["+toString(rs1)+"], ("+toString(rm)+" & 0xff));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
bgeu_rs1_rs2_imm
static InstructionDefinition bgeu_rs1_rs2_imm(ISA32_RISCV64, "bgeu",(uint32_t) 0x7063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//bgeu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+"] >= *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
ISA16_RISCV64
etiss::instr::InstructionGroup ISA16_RISCV64("ISA16_RISCV64", 16)
bge_rs1_rs2_imm
static InstructionDefinition bge_rs1_rs2_imm(ISA32_RISCV64, "bge",(uint32_t) 0x5063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//bge\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "if((etiss_int64)cast_1 >= (etiss_int64)cast_0)\n" "{\n" "etiss_int64 cast_2 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "choose1 = (etiss_int64)cast_2 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::S3
etiss_uint64 S3
Definition: RISCV64.h:62
c_slli_rs1_shamt
static InstructionDefinition c_slli_rs1_shamt(ISA16_RISCV64, "c.slli",(uint16_t) 0x2,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_5(12, 12);etiss_uint64 shamt_5=R_shamt_5.read(ba);shamt+=shamt_5<< 5;static BitArrayRange R_shamt_0(6, 2);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.slli\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rs1)+" == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "*((RISCV64*)cpu)->X["+toString(rs1)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] << "+toString(shamt)+");\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ETISS_CPU::cpuTime_ps
etiss_uint64 cpuTime_ps
simulation time of cpu
Definition: CPU.h:95
RISCV64
struct RISCV64 RISCV64
Definition: RISCV64.h:85
RISCV64Arch::newTimer
etiss::Plugin * newTimer(ETISS_CPU *cpu)
create a simple default timer implementaion instance for this architecture.
Definition: RISCV64Arch.cpp:234
RISCV64Arch::getMaximumInstructionSizeInBytes
virtual unsigned getMaximumInstructionSizeInBytes()
Definition: RISCV64Arch.cpp:203
RISCV64Arch::resetCPU
virtual void resetCPU(ETISS_CPU *cpu, etiss::uint64 *startpointer)
reset cpu (structure)
Definition: RISCV64Arch.cpp:67
or_rd_rs1_rs2
static InstructionDefinition or_rd_rs1_rs2(ISA32_RISCV64, "or",(uint32_t) 0x6033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//or\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] | *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
lbu_rd_imm_rs1_
static InstructionDefinition lbu_rd_imm_rs1_(ISA32_RISCV64, "lbu",(uint32_t) 0x4003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lbu\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint8 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,1);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)MEM_offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
beq_rs1_rs2_imm
static InstructionDefinition beq_rs1_rs2_imm(ISA32_RISCV64, "beq",(uint32_t) 0x63,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//beq\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+"] == *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::CSR
etiss_uint64 CSR[4096]
Definition: RISCV64.h:79
c_nop_
static InstructionDefinition c_nop_(ISA16_RISCV64, "c.nop",(uint16_t) 0x1,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.nop\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
c_lui_rd_imm
static InstructionDefinition c_lui_rd_imm(ISA16_RISCV64, "c.lui",(uint16_t) 0x6001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 imm=0;static BitArrayRange R_imm_17(12, 12);etiss_uint64 imm_17=R_imm_17.read(ba);imm+=imm_17<< 17;static BitArrayRange R_imm_12(6, 2);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.lui\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x20000)>>17 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294705152;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "if(imm_extended == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
lb_rd_imm_rs1_
static InstructionDefinition lb_rd_imm_rs1_(ISA32_RISCV64, "lb",(uint32_t) 0x3,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lb\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint8 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,1);\n" "etiss_int8 cast_1 = MEM_offs; \n" "if((etiss_int8)((etiss_uint8)cast_1 - 0x80) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint8)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
sh_rs2_imm_rs1_
static InstructionDefinition sh_rs2_imm_rs1_(ISA32_RISCV64, "sh",(uint32_t) 0x1023,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sh\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint16 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,2);\n" "if((offs + 2 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fmadd_d_rd_frs1_frs2_frs3
static InstructionDefinition fmadd_d_rd_frs1_frs2_frs3(ISA32_RISCV64, "fmadd.d",(uint32_t) 0x2000043,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmadd.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs3)+"] & 0xffffffffffffffff), (etiss_uint64)0, choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::FENCE
etiss_uint64 FENCE[4]
Definition: RISCV64.h:80
fcvt_lu_s_rd_frs1
static InstructionDefinition fcvt_lu_s_rd_frs1(ISA32_RISCV64, "fcvt.lu.s",(uint32_t) 0xc0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.lu.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_uint32 flags = 0;\n" "res = fcvt_32_64(unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]), (etiss_uint32)1, ("+toString(rm)+" & 0xff));\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)res;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::headers_
std::set< std::string > headers_
Definition: RISCV64Arch.h:146
bltu_rs1_rs2_imm
static InstructionDefinition bltu_rs1_rs2_imm(ISA32_RISCV64, "bltu",(uint32_t) 0x6063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//bltu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+"] < *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::A5
etiss_uint64 A5
Definition: RISCV64.h:58
fcvt_lu_d_rd_frs1
static InstructionDefinition fcvt_lu_d_rd_frs1(ISA32_RISCV64, "fcvt.lu.d",(uint32_t) 0xc2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.lu.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_int64 cast_0 = fcvt_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (etiss_uint32)1, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_srli_8_rs1_shamt
static InstructionDefinition c_srli_8_rs1_shamt(ISA16_RISCV64, "c.srli",(uint16_t) 0x8001,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_5(12, 12);etiss_uint64 shamt_5=R_shamt_5.read(ba);shamt+=shamt_5<< 5;static BitArrayRange R_shamt_0(6, 2);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.srli\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rs1_idx = 0;\n" "rs1_idx = "+toString(rs1)+" + 8;\n" "*((RISCV64*)cpu)->X[rs1_idx] = (*((RISCV64*)cpu)->X[rs1_idx] >> "+toString(shamt)+");\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
c_jr_rs1
static InstructionDefinition c_jr_rs1(ISA16_RISCV64, "c.jr",(uint16_t) 0x8002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.jr\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "cpu->instructionPointer = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
c_sd_8_rs2_uimm_8_rs1_
static InstructionDefinition c_sd_8_rs2_uimm_8_rs1_(ISA16_RISCV64, "c.sd",(uint16_t) 0xe000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(6, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.sd\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+" + 8];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ld_rd_imm_rs1_
static InstructionDefinition ld_rd_imm_rs1_(ISA32_RISCV64, "ld",(uint32_t) 0x3003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//ld\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_1 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fmul_d_rd_frs1_frs2
static InstructionDefinition fmul_d_rd_frs1_frs2(ISA32_RISCV64, "fmul.d",(uint32_t) 0x12000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmul.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmul_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sw_rs2_imm_rs1_
static InstructionDefinition sw_rs2_imm_rs1_(ISA32_RISCV64, "sw",(uint32_t) 0x2023,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
c_fsd_rs2_uimm_8_rs1_
static InstructionDefinition c_fsd_rs2_uimm_8_rs1_(ISA16_RISCV64, "c.fsd",(uint16_t) 0xa000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(6, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.fsd\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV64*)cpu)->F["+toString(rs2)+" + 8] & 0xffffffffffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
srli_rd_rs1_shamt
static InstructionDefinition srli_rd_rs1_shamt(ISA32_RISCV64, "srli",(uint32_t) 0x5013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(25, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srli\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] >> "+toString(shamt)+");\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
mulhsu_rd_rs1_rs2
static InstructionDefinition mulhsu_rd_rs1_rs2(ISA32_RISCV64, "mulhsu",(uint32_t) 0x2002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mulhsu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = ((etiss_int64)cast_0 * (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)(res >> 64);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmax_d_rd_frs1_frs2
static InstructionDefinition fmax_d_rd_frs1_frs2(ISA32_RISCV64, "fmax.d",(uint32_t) 0x2a001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmax.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "res = fsel_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmv_x_d_rd_frs1
static InstructionDefinition fmv_x_d_rd_frs1(ISA32_RISCV64, "fmv.x.d",(uint32_t) 0xe2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmv.x.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 cast_0 = ((RISCV64*)cpu)->F["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
lh_rd_imm_rs1_
static InstructionDefinition lh_rd_imm_rs1_(ISA32_RISCV64, "lh",(uint32_t) 0x1003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lh\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint16 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,2);\n" "etiss_int16 cast_1 = MEM_offs; \n" "if((etiss_int16)((etiss_uint16)cast_1 - 0x8000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint16)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
sra_rd_rs1_rs2
static InstructionDefinition sra_rd_rs1_rs2(ISA32_RISCV64, "sra",(uint32_t) 0x40005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sra\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 >> (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 64 - 1));\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fld_rd_imm_rs1_
static InstructionDefinition fld_rd_imm_rs1_(ISA32_RISCV64, "fld",(uint32_t) 0x3007,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fld\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "res = MEM_offs;\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
sraw_rd_rs1_rs2
static InstructionDefinition sraw_rd_rs1_rs2(ISA32_RISCV64, "sraw",(uint32_t) 0x4000503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sraw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "etiss_uint32 count = 0;\n" "etiss_int32 mask = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "mask = 31;\n" "count = ((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) & mask);\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "sh_val = ((etiss_int32)cast_0 >> count);\n" "etiss_int32 cast_1 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fsw_rs2_imm_xrs1_
static InstructionDefinition fsw_rs2_imm_xrs1_(ISA32_RISCV64, "fsw",(uint32_t) 0x2027,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64
Definition: RISCV64.h:41
ebreak_
static InstructionDefinition ebreak_(ISA32_RISCV64, "ebreak",(uint32_t) 0x100073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//ebreak\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "return ETISS_RETURNCODE_CPUFINISHED; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64::A7
etiss_uint64 A7
Definition: RISCV64.h:60
amoswap_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoswap_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoswap.w",(uint32_t) 0x800202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoswap.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
int32_t
signed int int32_t
Definition: stddef.h:15
uint16_t
unsigned short int uint16_t
Definition: stddef.h:22
mulw_rd_rs1_rs2
static InstructionDefinition mulw_rd_rs1_rs2(ISA32_RISCV64, "mulw",(uint32_t) 0x200003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mulw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) * (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
memset
__DEVICE__ void * memset(void *__a, int __b, size_t __c)
Definition: __clang_cuda_device_functions.h:1480
c_and_8_rd_8_rs2
static InstructionDefinition c_and_8_rd_8_rs2(ISA16_RISCV64, "c.and",(uint16_t) 0x8c61,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.and\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rd_idx = 0;\n" "rd_idx = "+toString(rd)+" + 8;\n" "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] & *((RISCV64*)cpu)->X["+toString(rs2)+" + 8]);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::initCodeBlock
virtual void initCodeBlock(etiss::CodeBlock &cb) const
called before instructions are translated for the code block
Definition: RISCV64Arch.cpp:222
divuw_rd_rs1_rs2
static InstructionDefinition divuw_rd_rs1_rs2(ISA32_RISCV64, "divuw",(uint32_t) 0x200503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//divuw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) != 0)\n" "{\n" "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) / (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = - 1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
uint64_t
unsigned long long int uint64_t
Definition: stddef.h:27
ETISS_CPU::resources
const char * resources[ETISS_MAX_RESOURCES]
names of resources
Definition: CPU.h:99
flt_s_rd_frs1_frs2
static InstructionDefinition flt_s_rd_frs1_frs2(ISA32_RISCV64, "flt.s",(uint32_t) 0xa0001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//flt.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)2);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)2);\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = fcmp_s((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffff), (etiss_uint32)2);\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomax.w",(uint32_t) 0xa000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomax.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = res1; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "if((etiss_int64)cast_2 < (etiss_int64)cast_1)\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
dii_
static InstructionDefinition dii_(ISA16_RISCV64, "dii",(uint16_t) 0x0,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//dii\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64::T6
etiss_uint64 T6
Definition: RISCV64.h:74
RISCV64::S11
etiss_uint64 S11
Definition: RISCV64.h:70
RISCV64::S6
etiss_uint64 S6
Definition: RISCV64.h:65
mulh_rd_rs1_rs2
static InstructionDefinition mulh_rd_rs1_rs2(ISA32_RISCV64, "mulh",(uint32_t) 0x2001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mulh\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "res = ((etiss_int64)cast_1 * (etiss_int64)cast_0);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)(res >> 64);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fle_d_rd_frs1_frs2
static InstructionDefinition fle_d_rd_frs1_frs2(ISA32_RISCV64, "fle.d",(uint32_t) 0xa2000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fle.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)1);\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::T5
etiss_uint64 T5
Definition: RISCV64.h:73
fsub_d_rd_frs1_frs2
static InstructionDefinition fsub_d_rd_frs1_frs2(ISA32_RISCV64, "fsub.d",(uint32_t) 0xa000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsub.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fsub_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_fld_rd_uimm_8_rs1_
static InstructionDefinition c_fld_rd_uimm_8_rs1_(ISA16_RISCV64, "c.fld",(uint16_t) 0x2000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(6, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(4, 2);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.fld\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "res = MEM_offs;\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+" + 8] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+" + 8] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64Arch::newMMU
etiss::mm::MMU * newMMU(ETISS_CPU *cpu)
It is an interface to instanciate a Memory Management Unit.
Definition: RISCV64Arch.cpp:246
c_fldsp_rd_uimm_x2_
static InstructionDefinition c_fldsp_rd_uimm_x2_(ISA16_RISCV64, "c.fldsp",(uint16_t) 0x2002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 uimm=0;static BitArrayRange R_uimm_5(12, 12);etiss_uint64 uimm_5=R_uimm_5.read(ba);uimm+=uimm_5<< 5;static BitArrayRange R_uimm_3(6, 5);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(4, 2);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.fldsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "res = MEM_offs;\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64::S5
etiss_uint64 S5
Definition: RISCV64.h:64
sret_
static InstructionDefinition sret_(ISA32_RISCV64, "sret",(uint32_t) 0x10200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sret\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->CSR[3088] = (((RISCV64*)cpu)->CSR[256] & 0x100)>>8;\n" "((RISCV64*)cpu)->CSR[256] ^= (((RISCV64*)cpu)->CSR[256] & 0x100);\n" "((RISCV64*)cpu)->CSR[256] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[256] & 0x20)>>4)) ^ (((RISCV64*)cpu)->CSR[256] & 0x2);\n" "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[321];\n" "((RISCV64*)cpu)->CSR[768]= ((RISCV64*)cpu)->CSR[256];\n" "((RISCV64*)cpu)->CSR[0]=((RISCV64*)cpu)->CSR[256];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
andi_rd_rs1_imm
static InstructionDefinition andi_rd_rs1_imm(ISA32_RISCV64, "andi",(uint32_t) 0x7013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//andi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 & imm_extended);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::A4
etiss_uint64 A4
Definition: RISCV64.h:57
lhu_rd_imm_rs1_
static InstructionDefinition lhu_rd_imm_rs1_(ISA32_RISCV64, "lhu",(uint32_t) 0x5003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lhu\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint16 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,2);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)MEM_offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoswap_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoswap_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoswap.d",(uint32_t) 0x800302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoswap.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ETISS_CPU::cpuCycleTime_ps
etiss_uint64 cpuCycleTime_ps
frequency of the cpu. use to allign e.g. memory delays
Definition: CPU.h:103
c_ld_8_rd_uimm_8_rs1_
static InstructionDefinition c_ld_8_rd_uimm_8_rs1_(ISA16_RISCV64, "c.ld",(uint16_t) 0x6000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(6, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(4, 2);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.ld\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
csrrc_rd_csr_rs1
static InstructionDefinition csrrc_rd_csr_rs1(ISA32_RISCV64, "csrrc",(uint32_t) 0x3073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrc\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 xrs1 = 0;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_uint64 xrd = 0;\n" "etiss_int64 writeMaskM = 0;\n" "xrd = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "xrs1 = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = xrd;\n" "}\n" "if("+toString(rs1)+" != 0)\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd & ~xrs1) & writeMask))&0xffffffffffffffff&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (xrd & ~xrs1)&0xffffffffffffffff;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::Plugin
base plugin class that provides access to different plugin functions if present
Definition: Plugin.h:76
uint64
etiss_uint64 uint64
Definition: 386-GCC.h:82
etiss_uint64
uint64_t etiss_uint64
Definition: types.h:96
fsgnjx_d_rd_frs1_frs2
static InstructionDefinition fsgnjx_d_rd_frs1_frs2(ISA32_RISCV64, "fsgnjx.d",(uint32_t) 0x22002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnjx.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 ONE = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 MSK1 = 0;\n" "ONE = 1;\n" "MSK1 = (ONE << 63);\n" "res = ((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff) ^ ((((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff) & MSK1));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fsgnjn_s_rd_frs1_frs2
static InstructionDefinition fsgnjn_s_rd_frs1_frs2(ISA32_RISCV64, "fsgnjn.s",(uint32_t) 0x20001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnjn.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((((RISCV64*)cpu)->F["+toString(rs1)+"] & 2147483647) | (~((RISCV64*)cpu)->F["+toString(rs2)+"] & -2147483648))&0xffffffffffffffff;\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = ((frs1 & 2147483647) | (~frs2 & -2147483648))&0xffffffff;\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmin_d_rd_frs1_frs2
static InstructionDefinition fmin_d_rd_frs1_frs2(ISA32_RISCV64, "fmin.d",(uint32_t) 0x2a000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmin.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "res = fsel_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)0);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomin.w",(uint32_t) 0x8000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomin.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = res1; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "if((etiss_int64)cast_2 > (etiss_int64)cast_1)\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
lr_d_rd_rs1
static InstructionDefinition lr_d_rd_rs1(ISA32_RISCV64, "lr.d",(uint32_t) 0x1000302f,(uint32_t) 0xf9f0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lr.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "((RISCV64*)cpu)->RES = offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
csrrs_rd_csr_rs1
static InstructionDefinition csrrs_rd_csr_rs1(ISA32_RISCV64, "csrrs",(uint32_t) 0x2073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrs\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 xrs1 = 0;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_uint64 xrd = 0;\n" "etiss_int64 writeMaskM = 0;\n" "xrd = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "xrs1 = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = xrd;\n" "}\n" "if("+toString(rs1)+" != 0)\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd | xrs1) & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (xrd | xrs1);\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_s_wu_rd_rs1
static InstructionDefinition fcvt_s_wu_rd_rs1(ISA32_RISCV64, "fcvt.s.wu",(uint32_t) 0xd0100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.wu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fcvt_s((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)3, ("+toString(rm)+" & 0xff));\n" "}\n" "else\n" "{\n" "res = fcvt_s((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)3, ("+toString(rm)+" & 0xff));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch.h
etiss_int64
int64_t etiss_int64
Definition: types.h:95
fclass_s_rd_frs1
static InstructionDefinition fclass_s_rd_frs1(ISA32_RISCV64, "fclass.s",(uint32_t) 0xe0001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fclass.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = fclass_s(unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]));\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fsgnj_d_rd_frs1_frs2
static InstructionDefinition fsgnj_d_rd_frs1_frs2(ISA32_RISCV64, "fsgnj.d",(uint32_t) 0x22000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnj.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 ONE = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 MSK1 = 0;\n" "etiss_int64 MSK2 = 0;\n" "ONE = 1;\n" "MSK1 = (ONE << 63);\n" "MSK2 = MSK1 - 1;\n" "res = (((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff) & MSK2) | ((((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff) & MSK1));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::mm::MM_ACCESS
MM_ACCESS
Definition: PageFaultVector.h:62
c_addi4spn_rd_imm
static InstructionDefinition c_addi4spn_rd_imm(ISA16_RISCV64, "c.addi4spn",(uint16_t) 0x0,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(4, 2);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 imm=0;static BitArrayRange R_imm_4(12, 11);etiss_uint64 imm_4=R_imm_4.read(ba);imm+=imm_4<< 4;static BitArrayRange R_imm_6(10, 7);etiss_uint64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_2(6, 6);etiss_uint64 imm_2=R_imm_2.read(ba);imm+=imm_2<< 2;static BitArrayRange R_imm_3(5, 5);etiss_uint64 imm_3=R_imm_3.read(ba);imm+=imm_3<< 3;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addi4spn\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(imm)+" == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = *((RISCV64*)cpu)->X[2] + "+toString(imm)+";\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoxor_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoxor_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoxor.w",(uint32_t) 0x2000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoxor.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "res2 = (res1 ^ *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fcvt_w_d_rd_frs1
static InstructionDefinition fcvt_w_d_rd_frs1(ISA32_RISCV64, "fcvt.w.d",(uint32_t) 0xc2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.w.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_int32 cast_0 = fcvt_64_32((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (etiss_uint32)0, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
wfi_
static InstructionDefinition wfi_(ISA32_RISCV64, "wfi",(uint32_t) 0x10500073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//wfi\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "return ETISS_RETURNCODE_CPUFINISHED; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::CodeBlock
A list of CodeSets.
Definition: CodePart.h:569
blt_rs1_rs2_imm
static InstructionDefinition blt_rs1_rs2_imm(ISA32_RISCV64, "blt",(uint32_t) 0x4063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//blt\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n" "{\n" "etiss_int64 cast_2 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "choose1 = (etiss_int64)cast_2 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::S0
etiss_uint64 S0
Definition: RISCV64.h:51
etiss::instr
Definition: ClassDefs.h:61
RISCV64Arch::getHeaders
virtual const std::set< std::string > & getHeaders() const
required headers (RISCV64.h)
Definition: RISCV64Arch.cpp:217
amoand_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoand_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoand.d",(uint32_t) 0x6000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoand.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "res2 = (res & *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ETISS_CPU::cycles
etiss_uint64 cycles[ETISS_MAX_RESOURCES]
how many cycles in each resource (including waiting)
Definition: CPU.h:101
RISCV64::T3
etiss_uint64 T3
Definition: RISCV64.h:71
RISCV64::S10
etiss_uint64 S10
Definition: RISCV64.h:69
fsd_rs2_imm_rs1_
static InstructionDefinition fsd_rs2_imm_rs1_(ISA32_RISCV64, "fsd",(uint32_t) 0x3027,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsd\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
c_subw_8_rd_8_rd_8_rs2
static InstructionDefinition c_subw_8_rd_8_rd_8_rs2(ISA16_RISCV64, "c.subw",(uint16_t) 0x9c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.subw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "res = (*((RISCV64*)cpu)->X["+toString(rd)+" + 8] & 0xffffffff) - (*((RISCV64*)cpu)->X["+toString(rs2)+" + 8] & 0xffffffff);\n" "etiss_int32 cast_0 = res; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
feq_s_rd_frs1_frs2
static InstructionDefinition feq_s_rd_frs1_frs2(ISA32_RISCV64, "feq.s",(uint32_t) 0xa0002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//feq.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)0);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)0);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::X
etiss_uint64 * X[32]
Definition: RISCV64.h:75
RISCV64::T0
etiss_uint64 T0
Definition: RISCV64.h:48
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